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On hamming product codes with type-II hybrid ARQ for on-chip interconnects

Authors:

Paul AmpaduAuthors Info & Claims

IEEE Transactions on Circuits and Systems Part I: Regular Papers, Volume 56, Issue 9

Pages 2042 - 2054

https://doi.org/10.1109/TCSI.2009.2026679

Published: 01 September 2009 Publication History

Abstract

We present hardware performance analyses of Hamming product codes combined with type-II hybrid automatic repeat request (HARQ), for on-chip interconnects. Input flit width and the number of rows in the product code message are investigated for their impact on the number of wires in the link, codec delay, reliability, and energy consumption. Analytical models are presented to estimate codec delay and residual flit error rate. The analyses are validated by comparison with simulation results. In a case study using H.264 video encoder in a network-on-chip environment, the method of combining Hamming product codes with type-II HARQ achieves several orders of magnitude improvement in residual flit error rate. For a given residual flit error rate requirement (e.g., 10^-20), this method yields up to 50% energy improvement over other error control methods in high-noise conditions.

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Chennakesavulu MJayachandra Prasad TSumalatha V(2018)Improved Performance of Error Controlling Codes Using Pass Transistor LogicCircuits, Systems, and Signal Processing10.1007/s00034-017-0596-437:3(1145-1161)Online publication date: 1-Mar-2018
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cover image IEEE Transactions on Circuits and Systems Part I: Regular Papers

IEEE Transactions on Circuits and Systems Part I: Regular Papers Volume 56, Issue 9

September 2009

250 pages

ISSN:1549-8328

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IEEE Press

Publication History

Published: 01 September 2009

Revised: 31 March 2009

Received: 18 December 2008

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Cited By

Dang KAhmed AAbdallah ATran X(2020)TSV-OCT: A Scalable Online Multiple-TSV Defects Localization for Real-Time 3-D-IC SystemsIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2019.294887828:3(672-685)Online publication date: 1-Mar-2020
https://dl.acm.org/doi/10.1109/TVLSI.2019.2948878
Chennakesavulu MJayachandra Prasad TSumalatha V(2018)Improved Performance of Error Controlling Codes Using Pass Transistor LogicCircuits, Systems, and Signal Processing10.1007/s00034-017-0596-437:3(1145-1161)Online publication date: 1-Mar-2018
https://dl.acm.org/doi/10.1007/s00034-017-0596-4
Aghaei BKhademzadeh AReshadi MBadie K(2017)Link TestingJournal of Electronic Testing: Theory and Applications10.1007/s10836-017-5646-033:2(209-225)Online publication date: 1-Apr-2017
https://dl.acm.org/doi/10.1007/s10836-017-5646-0
Maheswari MSeetharaman G(2014)Design of a novel error correction coding with crosstalk avoidance for reliable on-chip interconnection linkInternational Journal of Computer Applications in Technology10.1504/IJCAT.2014.05909749:1(80-88)Online publication date: 1-Feb-2014
https://dl.acm.org/doi/10.1504/IJCAT.2014.059097
Radetzki MFeng CZhao XJantsch A(2013)Methods for fault tolerance in networks-on-chipACM Computing Surveys10.1145/2522968.252297646:1(1-38)Online publication date: 11-Jul-2013
https://dl.acm.org/doi/10.1145/2522968.2522976
Yu QZhang MAmpadu P(2013)Addressing network-on-chip router transient errors with inherent information redundancyACM Transactions on Embedded Computing Systems10.1145/2485984.248599312:4(1-21)Online publication date: 3-Jul-2013
https://dl.acm.org/doi/10.1145/2485984.2485993
Huang PHwang W(2012)Self-calibrated energy-efficient and reliable channels for on-chip interconnection networksJournal of Electrical and Computer Engineering10.1155/2012/6970392012(1-1)Online publication date: 1-Jan-2012
https://dl.acm.org/doi/10.1155/2012/697039
Yu QAmpadu P(2012)Dual-layer adaptive error control for network-on-chip linksIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2011.215643620:7(1304-1317)Online publication date: 1-Jul-2012
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Nitta CFarrens MAkella VGaluzzi CCarro LMoshovos APrvulovic M(2011)Resilient microring resonator based photonic networksProceedings of the 44th Annual IEEE/ACM International Symposium on Microarchitecture10.1145/2155620.2155632(95-104)Online publication date: 3-Dec-2011
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Yu QZhang MAmpadu PMarculescu RKishinevsky MGinosar RChatha K(2011)Exploiting inherent information redundancy to manage transient errors in NoC routing arbitrationProceedings of the Fifth ACM/IEEE International Symposium on Networks-on-Chip10.1145/1999946.1999964(105-112)Online publication date: 1-May-2011
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