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Addressing network-on-chip router transient errors with inherent information redundancy

Authors:

Paul AmpaduAuthors Info & Claims

ACM Transactions on Embedded Computing Systems (TECS), Volume 12, Issue 4

Article No.: 105, Pages 1 - 21

https://doi.org/10.1145/2485984.2485993

Published: 03 July 2013 Publication History

Abstract

We exploit the inherent information redundancy in the control path of Network-on-Chip (NoC) routers to manage transient errors, preventing packet loss and misrouting. Outputs of the routing arbitration units in NoC routers can be used to determine arbitration failures, because the valid arbitration outputs are a subset of all possible values. This feature is exploited to detect and correct logic and register errors in the router arbitration control path. The proposed method is complementary to other error management methods for NoC routers. An analytical reliability model of our method is provided, including parameters such as logic unit size, different error rates for logic gates and registers, and the location of faulty elements. Compared to triple-modular redundancy (TMR), the proposed method improves the arbiter reliability by two orders of magnitude while reducing the total area and power by 43% and 64%, respectively. In the presented case studies, two traffic traces from the PARSEC benchmark suite are used to evaluate the average latency and energy consumption. Simulations performed on a 4× 4 NoC show that our method reduces the average latency by up to 50% and reduces average energy by up to 70% compared to other methods.

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Cited By

Dang KAhmed AAbdallah ATran X(2020)TSV-OCT: A Scalable Online Multiple-TSV Defects Localization for Real-Time 3-D-IC SystemsIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2019.294887828:3(672-685)Online publication date: Mar-2020
https://doi.org/10.1109/TVLSI.2019.2948878
Yu QZhang ZDofe J(2018)Investigating Reliability and Security of Integrated Circuits and Systems2018 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)10.1109/ISVLSI.2018.00029(106-111)Online publication date: Jul-2018
https://doi.org/10.1109/ISVLSI.2018.00029
Dang KBen Ahmed ATran XOkuyama YBen Abdallah A(2017)A Comprehensive Reliability Assessment of Fault-Resilient Network-on-Chip Using Analytical ModelIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2017.273600425:11(3099-3112)Online publication date: Nov-2017
https://doi.org/10.1109/TVLSI.2017.2736004
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Index Terms

Addressing network-on-chip router transient errors with inherent information redundancy
1. Hardware

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Information & Contributors

Information

Published In

cover image ACM Transactions on Embedded Computing Systems

ACM Transactions on Embedded Computing Systems Volume 12, Issue 4

Special Section on Wireless Health Systems, On-Chip and Off-Chip Network Architectures

June 2013

288 pages

ISSN:1539-9087

EISSN:1558-3465

DOI:10.1145/2485984

Issue’s Table of Contents

Copyright © 2013 ACM.

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New York, NY, United States

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ACM Journals for the Design of Smart and Connected Systems

Publication History

Published: 03 July 2013

Accepted: 01 September 2011

Revised: 01 July 2011

Received: 01 March 2011

Published in TECS Volume 12, Issue 4

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Cited By

Dang KAhmed AAbdallah ATran X(2020)TSV-OCT: A Scalable Online Multiple-TSV Defects Localization for Real-Time 3-D-IC SystemsIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2019.294887828:3(672-685)Online publication date: Mar-2020
https://doi.org/10.1109/TVLSI.2019.2948878
Yu QZhang ZDofe J(2018)Investigating Reliability and Security of Integrated Circuits and Systems2018 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)10.1109/ISVLSI.2018.00029(106-111)Online publication date: Jul-2018
https://doi.org/10.1109/ISVLSI.2018.00029
Dang KBen Ahmed ATran XOkuyama YBen Abdallah A(2017)A Comprehensive Reliability Assessment of Fault-Resilient Network-on-Chip Using Analytical ModelIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2017.273600425:11(3099-3112)Online publication date: Nov-2017
https://doi.org/10.1109/TVLSI.2017.2736004
Frey JYu Q(2017)A hardened network-on-chip design using runtime hardware Trojan mitigation methodsIntegration, the VLSI Journal10.1016/j.vlsi.2016.06.00856:C(15-31)Online publication date: 1-Jan-2017
https://dl.acm.org/doi/10.1016/j.vlsi.2016.06.008
Dang KMeyer MOkuyama YAbdallah A(2017)A low-overhead soft---hard fault-tolerant architecture, design and management scheme for reliable high-performance many-core 3D-NoC systemsThe Journal of Supercomputing10.1007/s11227-016-1951-073:6(2705-2729)Online publication date: 1-Jun-2017
https://dl.acm.org/doi/10.1007/s11227-016-1951-0
Dang KMeyer MOkuyama YAbdallah A(2016)Reliability Assessment and Quantitative Evaluation of Soft-Error Resilient 3D Network-on-Chip Systems2016 IEEE 25th Asian Test Symposium (ATS)10.1109/ATS.2016.37(161-166)Online publication date: Nov-2016
https://doi.org/10.1109/ATS.2016.37

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