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10.1109/DFT.2008.40guideproceedingsArticle/Chapter ViewAbstractPublication PagesConference Proceedingsacm-pubtype
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Adaptive Error Control for NoC Switch-to-Switch Links in a Variable Noise Environment

Published: 01 October 2008 Publication History

Abstract

We present an adaptive error control method for switch-to-switch links in a variable noise environment, to meet reliability requirements and achieve energy-efficiency. Unlike worst-case error correction coding (ECC), the proposed method is capable of selecting the most effective ECC scheme based on predicted link quality at runtime. Our method configures the ECC codec to obtain the desired error correction strength using a set of single-error correction (SEC) codes combined with interleaving. The method can effectively handle multi-cycle and adjacent multi-wire errors existing on switch-to-switch links. An experimental case study shows that the adaptive method can increase the energy-efficiency by up to 19% over a fixed ECC scheme, for a given residual flit error rate. Furthermore, energy reduction affected by different multi-wire and multi-cycle noise scenarios are compared.

Cited By

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  • (2021)Protection switching schemes and mapping strategies for fail-operational hard real-time NoCsMicroprocessors & Microsystems10.1016/j.micpro.2021.10438587:COnline publication date: 1-Nov-2021
  • (2014)Design of a novel error correction coding with crosstalk avoidance for reliable on-chip interconnection linkInternational Journal of Computer Applications in Technology10.1504/IJCAT.2014.05909749:1(80-88)Online publication date: 1-Feb-2014
  • (2013)Methods for fault tolerance in networks-on-chipACM Computing Surveys10.1145/2522968.252297646:1(1-38)Online publication date: 11-Jul-2013
  • Show More Cited By

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Published In

cover image Guide Proceedings
DFT '08: Proceedings of the 2008 IEEE International Symposium on Defect and Fault Tolerance of VLSI Systems
October 2008
492 pages
ISBN:9780769533650

Publisher

IEEE Computer Society

United States

Publication History

Published: 01 October 2008

Author Tags

  1. Error control coding
  2. Networks-on-Chip
  3. error detection
  4. fault tolerant
  5. single error correction

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Cited By

View all
  • (2021)Protection switching schemes and mapping strategies for fail-operational hard real-time NoCsMicroprocessors & Microsystems10.1016/j.micpro.2021.10438587:COnline publication date: 1-Nov-2021
  • (2014)Design of a novel error correction coding with crosstalk avoidance for reliable on-chip interconnection linkInternational Journal of Computer Applications in Technology10.1504/IJCAT.2014.05909749:1(80-88)Online publication date: 1-Feb-2014
  • (2013)Methods for fault tolerance in networks-on-chipACM Computing Surveys10.1145/2522968.252297646:1(1-38)Online publication date: 11-Jul-2013
  • (2010)Parallel processing for block ciphers on a fault tolerant networked processor arrayInternational Journal of High Performance Systems Architecture10.1504/IJHPSA.2010.0345372:3/4(156-167)Online publication date: 1-Aug-2010
  • (2010)A flexible parallel simulator for networks-on-chip with error controlIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2009.203435329:1(103-116)Online publication date: 1-Jan-2010
  • (2009)Fault tolerant mechanism to improve yield in NoCs using a reconfigurable routerProceedings of the 22nd Annual Symposium on Integrated Circuits and System Design: Chip on the Dunes10.1145/1601896.1601929(1-6)Online publication date: 31-Aug-2009
  • (2009)On hamming product codes with type-II hybrid ARQ for on-chip interconnectsIEEE Transactions on Circuits and Systems Part I: Regular Papers10.1109/TCSI.2009.202667956:9(2042-2054)Online publication date: 1-Sep-2009

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