IEEE Transactions on Circuits and Systems Part I: Regular Papers

Year 2009 marks the completion of 50 years of the invention of CORDIC (COordinate Rotation DIgital Computer) by Jack E. Volder. The beauty of CORDIC lies in the fact that by simple shift-add operations, it can perform several computing tasks such as the ...

In this paper, a signal processing methodology is proposed that performs delta-sigma (ΔΣ) analog-to-digital (A/D) conversion on voltage signals while implementing all the circuits in a digital CMOS logic style. This methodology, called time-mode (TM) ...

A signal acquisition system is presented for the recording of small signals in the presence of low-frequency interference. In a conventional design, high-pass filters precede the input stage to remove the impeding signals. However, filters limit the ...

This paper describes a technique for exploiting circuit instability to achieve baseband linear amplification. The input signal is periodically sampled by a first-order unstable circuit, and amplification is achieved by the exponentially growing natural ...

The self-powering, long-lasting, and functional features of embedded wireless microsensors appeal to an ever-expanding application space in monitoring, control, and diagnosis for military, commercial, industrial, space, and biomedical applications. ...

A previous cut-insertion theorem for linear circuits and its application to a generalization of the elementary feedback theory are further extended. The new theorem is based on the splitting of an arbitrary node into two nodes and on the insertion ...

This paper presents a universal architecture for Reed-Solomon (RS) error-and-erasure decoder. In comparison with other reconfigurable RS decoders, our universal approach based on Montgomery multiplication algorithm can support not only arbitrary block ...

An high-speed special function unit (SFU) is presented in this paper. The system supports the single-precision IEEE-754 floating-point standard and implements faithfully rounded reciprocal, square root, reciprocal square root, logarithm, and exponential ...

Power-gating is one of the most promising and widely adopted solutions for controlling sub-threshold leakage power in nanometer circuits. Although single-cycle power-mode transition reduces wake-up latency, it develops large discharge current spikes, ...

We consider the problem of adjusting speeds of multiple computer processors, sharing the same thermal environment, such as a chip or multichip package. We assume that the speed of each processor (and associated variables such as power supply voltage) ...

Modular exponentiation in public-key cryptosystems is usually achieved by repeated modular multiplications on large integers. Designing high-speed modular multiplication is thus very crucial to speed up the decryption/encryption process. In this paper, ...

As technology scales, the shrinking wire width increases the interconnect resistivity, while the decreasing interconnect spacing significantly increases the coupling capacitance. This paper proposes reducing the number of bus lines of the conventional ...

In modern digital systems, on-chip interconnects have become the system bottleneck, limiting the performance of high-speed clock distributions and data communications in terms of speed and power dissipation. An inverse signaling analysis is developed to ...

We present hardware performance analyses of Hamming product codes combined with type-II hybrid automatic repeat request (HARQ), for on-chip interconnects. Input flit width and the number of rows in the product code message are investigated for their ...

A digitally controlled oscillator (DCO) for the all-digital phase-locked loop (ADPLL) with both the wide frequency range and the high maximum frequency was proposed by using the interpolation scheme at both the coarse and fine delay blocks of the DCO. ...

This paper presents two-step design methodologies and performance analyses of finite-impulse response (FIR), all-pass, and infinite-impulse response (IIR) variable fractional delay (VFD) digital filters. In the first step, a set of fractional delay (FD) ...

Bandwidth mismatch between sample-and-hold (S/H) circuits in a time-interleaved analog-to-digital data converter (ADC) causes undesirable distortions in the output spectrum. To reduce these undesired spectral components, methods are needed to estimate ...

In this paper, a level-crossing analog-to-digital converter is described. It can convert audio bandwidth signals with high resolution using few threshold levels and digital interpolation. Samples are generated at nonuniform time intervals and then ...

In this paper, a general complex switched network (CSN) model is presented. The model is more general than those in the literatures in which it contains switching behaviors on both its nodes and topology configuration. Robust stabilization of directed ...

We solve the problem of set-point (respectively, tracking) control of a permanent-magnet synchronous motor via linear time-invariant (respectively, time varying) control. Our control approach is based on the physical properties of the machine: inherent ...

An N-symbol discrete Fourier transform (N-DFT) processor based on analog CMOS current mirrors that operate in the strong inversion region is presented. It is shown that transistor mismatch can be modeled as an input-referred noise source that can be ...

Switched-capacitor (SC) converters are a type of variable structure systems. The conventional approach of maintaining regulation in these converters is a feedback control developed from linear systems theory, and it is based on the approximate small-...