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Synchronous path analysis in MOS circuit simulator

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Vishwani D. AgrawalAuthors Info & Claims

DAC '82: Proceedings of the 19th Design Automation Conference

Pages 629 - 635

Published: 01 January 1982 Publication History

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Abstract

For verifying the timing performance of synchronous MOS circuits a path analysis facility has been developed in the MOTIS (MOS Timing Simulator) system. This path analysis traces the clock signals to the latches in the circuit, computes the clock skews and then performs a path search analysis between all latches. For the paths between clocked latches, the timing constraints are determined using the clock skews and the operating frequency. The paths that do not satisfy these constraints are identified as problem paths. Such an analysis does not require a prior generation of circuit stimuli that are necessary for simulation. In terms of complexity also, it is simpler than simulation.

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Cited By

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Cheung EHsieh HBalarin FGebotys CMartin G(2008)Software optimization for MPSoCProceedings of the 6th IEEE/ACM/IFIP international conference on Hardware/Software codesign and system synthesis10.1145/1450135.1450146(43-48)Online publication date: 19-Oct-2008
https://dl.acm.org/doi/10.1145/1450135.1450146
Chakraborty TAgrawal V(1997)Effective Path Selection for Delay Fault Testing of Sequential CircuitsProceedings of the 1997 IEEE International Test Conference10.5555/844384.845817Online publication date: 1-Nov-1997
https://dl.acm.org/doi/10.5555/844384.845817
Papaefthymiou MRandall KDunlop A(1993)TIMProceedings of the 30th international Design Automation Conference10.1145/157485.164998(497-502)Online publication date: 1-Jul-1993
https://dl.acm.org/doi/10.1145/157485.164998
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Index Terms

Synchronous path analysis in MOS circuit simulator
1. Hardware
  1. Communication hardware, interfaces and storage
    1. Buses and high-speed links
2. Mathematics of computing
  1. Discrete mathematics
    1. Graph theory
      1. Paths and connectivity problems
  2. Mathematical analysis
    1. Integral equations

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DAC '82: Proceedings of the 19th Design Automation Conference

January 1982

919 pages

ISBN:0897910206

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IEEE Press

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Published: 01 January 1982

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Cheung EHsieh HBalarin FGebotys CMartin G(2008)Software optimization for MPSoCProceedings of the 6th IEEE/ACM/IFIP international conference on Hardware/Software codesign and system synthesis10.1145/1450135.1450146(43-48)Online publication date: 19-Oct-2008
https://dl.acm.org/doi/10.1145/1450135.1450146
Chakraborty TAgrawal V(1997)Effective Path Selection for Delay Fault Testing of Sequential CircuitsProceedings of the 1997 IEEE International Test Conference10.5555/844384.845817Online publication date: 1-Nov-1997
https://dl.acm.org/doi/10.5555/844384.845817
Papaefthymiou MRandall KDunlop A(1993)TIMProceedings of the 30th international Design Automation Conference10.1145/157485.164998(497-502)Online publication date: 1-Jul-1993
https://dl.acm.org/doi/10.1145/157485.164998
Agrawal PAgrawal VSeth SMusgrave G(1992)DynaTAPPProceedings of the conference on European design automation10.5555/159754.161743(138-141)Online publication date: 1-Nov-1992
https://dl.acm.org/doi/10.5555/159754.161743
Lin ILudwig JEng KSchweikert D(1992)Analyzing cycle stealing on synchronous circuits with level-sensitive latchesProceedings of the 29th ACM/IEEE Design Automation Conference10.5555/113938.149504(393-398)Online publication date: 1-Jul-1992
https://dl.acm.org/doi/10.5555/113938.149504
Chakraborty TAgrawal VBushnell MSchweikert D(1992)Delay fault models and test generation for random logic sequential circuitsProceedings of the 29th ACM/IEEE Design Automation Conference10.5555/113938.117295(165-172)Online publication date: 1-Jul-1992
https://dl.acm.org/doi/10.5555/113938.117295
Sakallah KMudge TOlukotun OSmith R(1991)Analysis and design of latch-controlled synchronous digital circuitsProceedings of the 27th ACM/IEEE Design Automation Conference10.1145/123186.123237(111-117)Online publication date: 3-Jan-1991
https://dl.acm.org/doi/10.1145/123186.123237
Bays LChen CFields EGadenz RHays WMoscovitz HSzymanski T(1989)Post-Layout Verification of the WE DSP32 Digital Signal ProcessorIEEE Design & Test10.1109/54.203906:1(56-66)Online publication date: 1-Jan-1989
https://dl.acm.org/doi/10.1109/54.20390
Li WReddy SSahni SShaklee DNewton A(1988)On path selection in combinational logic circuitsProceedings of the 25th ACM/IEEE Design Automation Conference10.5555/285730.285753(142-147)Online publication date: 1-Jun-1988
https://dl.acm.org/doi/10.5555/285730.285753
Dunlop AAgrawal VDeutsch DJukl MKazak P(1988)Chip layout optimization using critical path weightingPapers on Twenty-five years of electronic design automation10.1145/62882.62915(278-281)Online publication date: 1-Jun-1988
https://dl.acm.org/doi/10.1145/62882.62915
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Abstract

References

Cited By

Index Terms

Recommendations

Extended sequential logic for synchronous circuit optimization and its applications

Switch-level timing models in the MOS simulator BRASIL

A workstation-mixed model circuit simulator

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