Cited By
View all- Adler DShaklee DNewton A(1988)A dynamically-directed switch model for MOS logic simulationProceedings of the 25th ACM/IEEE Design Automation Conference10.5555/285730.285812(506-511)Online publication date: 1-Jun-1988
A workstation-mixed model circuit simulator
Abstract
A new mixed mode simulator is described, which combines a behavioral timing simulator, a switch level simulator, and a new circuit-level simulator based upon the ADEPT timing simulation algorithm. These simulation algorithms are combined into a single, consistent, interactive MOS simulator. In addition, STAFAN fault simulation is provided at the transistor level to grade vectors to be used in the testing phase of design. In this paper, each algorithm is described as well as the interfacing required between each of the simulation methods.
Several examples are presented to demonstrate the utility of the L-Simulator. Circuit simulation is performed on a wide range of CMOS counter sizes, from 2 to 32 bits, showing tremendous reductions in CPU time as compared to SPICE, without loss in accuracy. A novel multi-mode simulation facility is also introduced, further decreasing the CPU time requirements for simulation. A second example shows how the performance and area of a CMOS latch is optimized using circuit modification techniques during simulation. Finally, a 73,200 transistor design of an 8051-like CPU is simulated in behavioral, switch level, and finally in circuit/mixed modes.
References
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Deutsch, J.T. and Newton, A.R., A Multiprocessor Implemente~tion of Relaxation-Based Electrical Circuit Simula,tion, IEEE DAC, (June 1984).
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Lathrop, R.H. and Kirk, R.S., An Extensible Object-Oriented Mixed-Mode Functional Simulation System, IEEE DA C, (June 1985).
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Bryant R.E, MOSSIM: A Switch-Level Simulator for MOS LSI, IEEE DAC, (June 1981).
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Szygenda, S.A., TEGAS2-Anatomy of a General Purpose Test Generation and Simulation System for Digital Logic, IEEE DAC, (June 1972).
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Chawla, }=I.R., et a}, MOTIS-An MOS Timing Simulator, IEEE Trans. Circuits Sy$t., (Dec 1975).
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Kleckner, J.E., Advanced Mixed Mode Simulation Techniques, PhD Thesis, University of California, Berkeley, (June 1984).
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Freston, P.A. and Smith, R.J., Workstation Design for VLSI Layout, IEEE ICCD, (Nov 1983).
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Sakallah, K.A., SAMSON: Mixed Simulation of Electronic integrated Circuits, PhD Thesis, Carnegie-Mellon University, (May 1983).
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Odryna, P., Simulator Merges Speed of Logic Verification with Circuit-Level Accuracy, Electronic Design, (Nov 28, 1985).
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Odryna, P. and Nassif, S.R., The ADEPT Timing Simulation Algorithm, VLSI System Design, (March 1986).
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Sakallah, K.A. and Director, S.W., An Activity- Directed Circuit Simulation Algorithm, Proc. IEEE ICCC, IEEE, (1980).
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Matheson, T.G., Christensen, C.C., and Burich, M.R., A Software Environment for Building Core- Microprocessor Compilers, ICCD, (Oct 1985).
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Vladimirescu, A. and Liu, S., Simulation of MOS Integrated Circuits using SPICE2, Memorandum ERL-MSO/7, Electronics Research Laboratory, University of California, Berkeley, (Oct 1980).
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Kim, Y.H., et ~1., Electrical-Logic Simulation, IEEE ICCAD, EE/CS, University of California, Berkeley, (1984).
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Newton, A.R., Computer :Aided Design of VLSI, Proc of IEEE on CAD, Vol 69 #10, IEEE, (Oct (1981).
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Dumlugol, D., et, al., Local Relaxation Algorit, hms for Event-Driven Simulation of MOS Networks Including Assignable Delay Modeling, IEEE Trans. on CAD, (July I983).
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Jain, S.I(. ~nd Agrawal, V.D., STA.FAN: An Alt, ernative to Fault Simulation, 1EEE DAC, (June 1984).
Index Terms
- A workstation-mixed model circuit simulator
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View all- Adler DShaklee DNewton A(1988)A dynamically-directed switch model for MOS logic simulationProceedings of the 25th ACM/IEEE Design Automation Conference10.5555/285730.285812(506-511)Online publication date: 1-Jun-1988
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