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A multiple delay simulator for MOS LSI circuits

Published: 23 June 1980 Publication History

Abstract

This paper describes a multiple delay simulator for MOS LSI circuits. The basic primitives for this simulator are MOS transistor structures where the transistors are evaluated logically. Integer rise and fall delays are associated with each transition and these delays are computed automatically based on device characteristics and circuit capacitances. The simulator has been extensively used for the design verification of production LSI chips.

References

[1]
L. W. Nagel, "SPICE2: A Computer Program to Simulate Semiconductor Circuits," Memo No. ERL-M520, Univ. of California, Berkeley, May 9, 1975.
[2]
W. T. Weeks et al, "Algorithms for ASTAP - A Network Analysis Program," IEEE Trans. Circuit Theory, Vol. CT-20, pp. 628-634, November 1973.
[3]
B. R. Chawla, H. K. Gummel, and P. Kozak, "MOTIS - An MOS Timing Simulator," IEEE Trans. on Circuits & Systems, Vol. CAS-22, pp. 901-910, December 1975.
[4]
J. D. Crawford, M. Y. Hsueh, A. R. Newton and D. O. Pederson, "MOTIS-C User's Guide," Electronics Research Laboratory, University of California, Berkeley, June 1978.
[5]
H. Y. Chang, G. W. Smith, Jr., and R. B. Walford, "LAMP: System Description", B.S.T.J., Vol. 53, pp. 1431-1499, October 1974.
[6]
S. A. Szygenda and E. W. Thompson, "Digital Logic Simulation in a Time Based, Table-Driven Environment, Part-1. Design Verification," Computer, Vol. 8, pp. 24-36, March 1975.
[7]
S. G. Chappell, P. R. Menon, J. F. Pellegrin and A. M. Showe, "Functional Simulation in LAMP System," Journal of Design Automation Fault Tolerant Computing Vol. 1, No. 3, May 1977.
[8]
R. E. Swanson, Z. Navabis and F. J. Hill: "An AHPL Compiler/Simulator System," Proceedings Sixth Texas Conference on Computing System, Austin, Texas, November 14-15, 1977.
[9]
P. Kozak, H. K. Gummel, and B. R. Chawla, "Operational Features of an MOS Timing Simulator," Proceedings of 12th Design Automation Conference, Boston, MA, June 23-25, 1975, pp. 95-101.
[10]
D. J. Pilling and H. B. Sun, "Computer-aided Prediction of Delays in LSI Logic Systems," in Proc. 10th ACM-IEEE Design Automation Workshop, Portland, Oregon, June 1973, pp. 182-186.
[11]
A. Koppel, S. Shah, and P. Puri, "A High Performance Delay Calculation Software System for MOS-FET Digital Logic Chips," Proceedings of 15th Design Automation Conference, Las Vegas, Nevada, June 19-21, 1978, pp. 405-417.

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cover image ACM Conferences
DAC '80: Proceedings of the 17th Design Automation Conference
June 1980
642 pages
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Published: 23 June 1980

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  • (1997)Selection of Voltage Thresholds for Delay MeasurementAnalog Integrated Circuits and Signal Processing10.1023/A:100827412395814:1-2(9-28)Online publication date: 1-Sep-1997
  • (1997)Selection of Voltage Thresholds for Delay MeasurementAnalog Design Issues in Digital VLSI Circuits and Systems10.1007/978-1-4615-6101-9_2(9-28)Online publication date: 1997
  • (1991)ILLIADSProceedings of the 28th ACM/IEEE Design Automation Conference10.1145/127601.127616(20-25)Online publication date: 1-Jun-1991
  • (1988)A fault simulator for MOS LSI circuitsPapers on Twenty-five years of electronic design automation10.1145/62882.62935(436-445)Online publication date: 1-Jun-1988
  • (1988)Chip layout optimization using critical path weightingPapers on Twenty-five years of electronic design automation10.1145/62882.62915(278-281)Online publication date: 1-Jun-1988
  • (1988)Behavioral-Level Fault SimulationIEEE Design & Test10.1109/54.79615:3(31-42)Online publication date: 1-May-1988
  • (1984)An MOS digital network model on a modified thevenin equivalent for logic simulationProceedings of the 21st Design Automation Conference10.5555/800033.800852(549-555)Online publication date: 25-Jun-1984
  • (1984)A VLSI FSM design systemProceedings of the 21st Design Automation Conference10.5555/800033.800834(434-440)Online publication date: 25-Jun-1984
  • (1984)A high level synthesis tool for MOS chip designProceedings of the 21st Design Automation Conference10.5555/800033.800813(308-314)Online publication date: 25-Jun-1984
  • (1984)Chip layout optimization using critical path weightingProceedings of the 21st Design Automation Conference10.5555/800033.800787(133-136)Online publication date: 25-Jun-1984
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