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On path selection in combinational logic circuits

Authors:

Sudhakar M. Reddy,

Sartaj SahniAuthors Info & Claims

DAC '88: Proceedings of the 25th ACM/IEEE Design Automation Conference

Pages 142 - 147

Published: 01 June 1988 Publication History

Abstract

In order to ascertain correct operation of digital logic circuits it is necessary to verify correct functional operation as well as correct operation at desired clock rates. To ascertain correct operation at desired clock rates signal propagation delays along a set of selected paths are verified to fall within allowed limits by applying appropriate stimuli. Earlier it was suggested that an appropriate set of paths to test would be the one that includes at least one path, with maximum modeled delay, for each circuit lead or gate input. In this paper, algorithms to select such sets of paths with minimum cardinality are given.

References

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G.L Smith, "Model for Delay F~ults B~,sed Upon P~ths," Proc. 1985 Int'l. Test Cnf., Nov. 198.5, pp. 342-349.

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Y.K. Malaiyu and R. N~rayanaswamy, "Testing for Timing Faults in Synchronous Sequent, iul Integrated Circuit~," Froc. 1988 Int'l. Test C, or(f. Oct. 1983, pp. 560- 571.

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K.D. Wagner, "Delay Testing of Digital Circuit.s Using Pseudorundom Input, Sequences," Center for Reliable Computing Report 85-12, revised March 1986. Stamford University.

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J. Savir and W.H. Mcanney, "Random Pa.ttern Testabilit, y of Dela, y Faults," Proc. i980 lnt'l. Tc~'t C@, Sept,. 1986, pp. 263-273.

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C.J. Lin and S.M. Reddy, "On Dela.v Fa.ul! Testing in Logic Circuits," IEEE Trans. C.4D. Sept. 1987, pp. 694- 703

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F. Brglez amd H. Fujiwara, "Neutral Net.list of Ten Combinational Benchma.rk Circuits and a Target Transla.tor in FORTRAN," Proc. IEEE Int. Syrup. Circttils 8; Systems. June 1985

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E. L~wler, Combinatorial Oplimiz, tion: Networks and Matroids. Holt, Rinehaort, and \Viust.on. 1.976

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R.B. Hitchcock, St., "Timing \%rifi~-~tt.ion and t.lle Timing Analysis Program," Proc. A6'M IEEE 19th De.~ign Automation Conf., June 1982, pp. 594-604.

Digital Library

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V.D. Agrawal, "Synchronous Pa.th Analysis ill lk~{OS (!ircuit Simulator," Proc. ACA'I IEEE I9lh De~i9~ At~tomttion Co.n.f, June 1982, pp. 629-635.

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H.K. A1-Hussein, "Path-Del;ty Coml)utation Algorithms for VLSI Systems," VLSI Design, Fet)ruarv 1985. pp. 86-91.

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S. Patoil, "An Automatic Test Pat, tern Genera for for Delay Faults in Logic Circuits," ~1.,5". Thesis. Dep,rtmerit of Electrical and Computer Engineering. (;niversity o.f Iowa. May 1987.

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H.T. Liu and C.R. Kime. "A Dela.y Test Generation System for Combinational logic," Tech Report. Dept. o.f Elec. ~ Comp. En.g, University of IVisconsin.Madison. August 1987.

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R.B. Hitchcoek, G.L. Smith ~n(1 D.D. Cheng, "Timing Analysis of Computer Hardware," IBM J. Research ~z Development, vol. 26, No. 1, Ja.n. 1982, pp. 100-108.

Digital Library

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S.M. Reddy, C.J. Liu, and S. Patil. " An Autolnatic Test, Pattern Generator for the Detection of Path Delay Faults," Proc. int. Conf. on Computer Aided Design, November 1987, .pp 284-287

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E.J. MeCluskey, Logic Design Principles, Prentine-Ha|l, 1986.

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W.N. Li, S.M. Reddy, end S. Sahni, "On Path Selection In Combinational Logic Circuits," TR 87-50 Compttter Science Department, University of l~Iin.ne,~ota, Oct.ober 1087.

Cited By

Jayabharathi RLee KAbraham J(1997)A Novel Solution for Chip-Level Functional Timing VerificationProceedings of the 15th IEEE VLSI Test Symposium10.5555/832297.836396Online publication date: 27-Apr-1997
https://dl.acm.org/doi/10.5555/832297.836396
Ravikumar CAgrawal NAgarwal P(1997)Hierarchical Delay Test GenerationJournal of Electronic Testing: Theory and Applications10.1023/A:100826760883810:3(231-244)Online publication date: 1-Jun-1997
https://dl.acm.org/doi/10.1023/A%3A1008267608838
Hajjar AGreiner AMarbot RKiani PAmbler TJess JDe Man H(1991)TASProceedings of the conference on European design automation10.5555/951513.951570(261-265)Online publication date: 25-Feb-1991
https://dl.acm.org/doi/10.5555/951513.951570

Index Terms

On path selection in combinational logic circuits
1. Hardware
2. Mathematics of computing
  1. Discrete mathematics

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Information & Contributors

Information

Published In

cover image ACM Conferences

DAC '88: Proceedings of the 25th ACM/IEEE Design Automation Conference

June 1988

730 pages

ISBN:0818688645

Chairmen:
Dennis W. Shaklee
AT&T/ISL, Denver, CO
,
A. Richard Newton
Univ. of California, Berkeley

Sponsors

SIGDA: ACM Special Interest Group on Design Automation
IEEE: Institute of Electrical and Electronics Engineers

Publisher

IEEE Computer Society Press

Washington, DC, United States

Publication History

Published: 01 June 1988

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DAC88

Sponsor:

SIGDA
IEEE

DAC88: Design Automation Conference

June 12 - 15, 1988

New Jersey, Atlantic City, USA

Acceptance Rates

DAC '88 Paper Acceptance Rate 125 of 400 submissions, 31%;

Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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DAC '25

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62nd ACM/IEEE Design Automation Conference

June 22 - 26, 2025

San Francisco , CA , USA

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Citations

Cited By

Jayabharathi RLee KAbraham J(1997)A Novel Solution for Chip-Level Functional Timing VerificationProceedings of the 15th IEEE VLSI Test Symposium10.5555/832297.836396Online publication date: 27-Apr-1997
https://dl.acm.org/doi/10.5555/832297.836396
Ravikumar CAgrawal NAgarwal P(1997)Hierarchical Delay Test GenerationJournal of Electronic Testing: Theory and Applications10.1023/A:100826760883810:3(231-244)Online publication date: 1-Jun-1997
https://dl.acm.org/doi/10.1023/A%3A1008267608838
Hajjar AGreiner AMarbot RKiani PAmbler TJess JDe Man H(1991)TASProceedings of the conference on European design automation10.5555/951513.951570(261-265)Online publication date: 25-Feb-1991
https://dl.acm.org/doi/10.5555/951513.951570

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