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Article

Testing embedded-core based system chips

Authors:

Yervant Zorian,

Erik Jan Marinissen,

Sujit DeyAuthors Info & Claims

ITC '98: Proceedings of the 1998 IEEE International Test Conference

Page 130

Published: 18 October 1998 Publication History

Abstract

Advances in semiconductor process and design technology enable the design of complex system chips. Traditional IC design,in which every circuit is designed from scratch and reuse is limited to standard-cell libraries, is more and more replaced bya design style based on embedding large reusable modules, the so-called cores. This core-based design poses a series of newchallenges, especially in the domains of manufacturing test and design validation and debug. This paper provides an overviewof current industrial practices as well as academic research in these areas. We also discuss industry-wide efforts by VSIA andIEEE P1500 and describe the challenges for future research.

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Cited By

Trock DFisette RFanucci LTeich J(2016)Recursive hierarchical DFT methodology with multi-level clock control and scan pattern retargetingProceedings of the 2016 Conference on Design, Automation & Test in Europe10.5555/2971808.2972071(1128-1131)Online publication date: 14-Mar-2016
https://dl.acm.org/doi/10.5555/2971808.2972071
Huang XMathew JShafik RBhattacharjee SPradhan DMacii E(2013)A fast and Effective DFT for test and diagnosis of power switches in SoCsProceedings of the Conference on Design, Automation and Test in Europe10.5555/2485288.2485552(1089-1092)Online publication date: 18-Mar-2013
https://dl.acm.org/doi/10.5555/2485288.2485552
Marinissen EDe Micheli GAl-Hashimi BMueller WMacii E(2010)Testing TSV-based three-dimensional stacked ICsProceedings of the Conference on Design, Automation and Test in Europe10.5555/1870926.1871336(1689-1694)Online publication date: 8-Mar-2010
https://dl.acm.org/doi/10.5555/1870926.1871336
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Information & Contributors

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Published In

cover image Guide Proceedings

ITC '98: Proceedings of the 1998 IEEE International Test Conference

October 1998

753 pages

ISBN:0780350936

Publisher

IEEE Computer Society

United States

Publication History

Published: 18 October 1998

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Cited By

Trock DFisette RFanucci LTeich J(2016)Recursive hierarchical DFT methodology with multi-level clock control and scan pattern retargetingProceedings of the 2016 Conference on Design, Automation & Test in Europe10.5555/2971808.2972071(1128-1131)Online publication date: 14-Mar-2016
https://dl.acm.org/doi/10.5555/2971808.2972071
Huang XMathew JShafik RBhattacharjee SPradhan DMacii E(2013)A fast and Effective DFT for test and diagnosis of power switches in SoCsProceedings of the Conference on Design, Automation and Test in Europe10.5555/2485288.2485552(1089-1092)Online publication date: 18-Mar-2013
https://dl.acm.org/doi/10.5555/2485288.2485552
Marinissen EDe Micheli GAl-Hashimi BMueller WMacii E(2010)Testing TSV-based three-dimensional stacked ICsProceedings of the Conference on Design, Automation and Test in Europe10.5555/1870926.1871336(1689-1694)Online publication date: 8-Mar-2010
https://dl.acm.org/doi/10.5555/1870926.1871336
Yoneda TFujiwara HSciuto D(2008)Wrapper and TAM co-optimization for reuse of SoC functional interconnectsProceedings of the conference on Design, automation and test in Europe10.1145/1403375.1403704(1366-1369)Online publication date: 10-Mar-2008
https://dl.acm.org/doi/10.1145/1403375.1403704
Sinanoglu OMarinissen ESciuto D(2008)Analysis of the test data volume reduction benefit of modular SOC testingProceedings of the conference on Design, automation and test in Europe10.1145/1403375.1403421(182-187)Online publication date: 10-Mar-2008
https://dl.acm.org/doi/10.1145/1403375.1403421
Song JYi HHan JPark S(2007)An efficient link controller for test access to IP core-based embedded system chipsProceedings of the 12th Asia-Pacific conference on Advances in Computer Systems Architecture10.5555/2392163.2392178(139-150)Online publication date: 23-Aug-2007
https://dl.acm.org/doi/10.5555/2392163.2392178
Wielage PMarinissen EAltheimer MWouters CLauwereins RMadsen J(2007)Design and DfT of a high-speed area-efficient embedded asynchronous FIFOProceedings of the conference on Design, automation and test in Europe10.5555/1266366.1266551(853-858)Online publication date: 16-Apr-2007
https://dl.acm.org/doi/10.5555/1266366.1266551
Yoneda TImanishi MFujiwara HLauwereins RMadsen J(2007)Interactive presentation: An SoC test scheduling algorithm using reconfigurable union wrappersProceedings of the conference on Design, automation and test in Europe10.5555/1266366.1266415(231-236)Online publication date: 16-Apr-2007
https://dl.acm.org/doi/10.5555/1266366.1266415
Sinanoglu OPetrov TLauwereins RMadsen J(2007)A non-intrusive isolation approach for soft coresProceedings of the conference on Design, automation and test in Europe10.5555/1266366.1266375(27-32)Online publication date: 16-Apr-2007
https://dl.acm.org/doi/10.5555/1266366.1266375
Lee JTehranipoor MPatel CPlusquellic J(2007)Securing Designs against Scan-Based Side-Channel AttacksIEEE Transactions on Dependable and Secure Computing10.1109/TDSC.2007.702154:4(325-336)Online publication date: 1-Oct-2007
https://dl.acm.org/doi/10.1109/TDSC.2007.70215
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