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research-article

Macro Testing: Unifying IC And Board Test

Published: 01 November 1986 Publication History

Abstract

Historically, IC testing and board testing have been considered two separate subjects. However, today's increasing complexityin both design and technology has given rise to a number of efforts to produce a consistent test strategy that smoothly couplesboth types of testing. This article describes one such effort by Philips, a design for testability methodology for semicustomVLSI circuits. The methodology is based on the partitioning of a design into testable macros, hence the term ?macro testing.?The challenges in this approach are the partitioning itself, the selection of a test technique suited to the separate macrosand the chip's architecture, the execution of a macro test independent of its environment, and the assembly of macro testsinto a chip test.

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  • (2007)Design and DfT of a high-speed area-efficient embedded asynchronous FIFOProceedings of the conference on Design, automation and test in Europe10.5555/1266366.1266551(853-858)Online publication date: 16-Apr-2007
  • (2006)InTeRailIEEE Transactions on Computers10.1109/TC.2006.2755:2(137-149)Online publication date: 1-Feb-2006
  • (2002)The Role of Test Protocols in Automated Test Generation for Embedded-Core-Based System ICsJournal of Electronic Testing: Theory and Applications10.1023/A:101654560791518:4-5(435-454)Online publication date: 1-Aug-2002
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  1. Macro Testing: Unifying IC And Board Test

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          Published In

          cover image IEEE Design & Test
          IEEE Design & Test  Volume 3, Issue 6
          November 1986
          48 pages

          Publisher

          IEEE Computer Society Press

          Washington, DC, United States

          Publication History

          Published: 01 November 1986

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          Cited By

          View all
          • (2007)Design and DfT of a high-speed area-efficient embedded asynchronous FIFOProceedings of the conference on Design, automation and test in Europe10.5555/1266366.1266551(853-858)Online publication date: 16-Apr-2007
          • (2006)InTeRailIEEE Transactions on Computers10.1109/TC.2006.2755:2(137-149)Online publication date: 1-Feb-2006
          • (2002)The Role of Test Protocols in Automated Test Generation for Embedded-Core-Based System ICsJournal of Electronic Testing: Theory and Applications10.1023/A:101654560791518:4-5(435-454)Online publication date: 1-Aug-2002
          • (2001)Test and Debug Strategy of the PNX8525 Nexperia" Digital Video Platform System ChipProceedings of the 2001 IEEE International Test Conference10.5555/839296.843710Online publication date: 30-Oct-2001
          • (1998)Testing embedded-core based system chipsProceedings of the 1998 IEEE International Test Conference10.5555/648020.745773Online publication date: 18-Oct-1998
          • (1994)TenIEEE Design & Test10.1109/MDT.1994.30384311:3(6-16)Online publication date: 1-Jul-1994
          • (1991)Automated test pattern generation for the Cathedral-II/2nd architectural synthesis environmentProceedings of the conference on European design automation10.5555/951513.951559(208-213)Online publication date: 25-Feb-1991
          • (1990)Designing and Implementing an Architecture with Boundary ScanIEEE Design & Test10.1109/54.468897:1(9-19)Online publication date: 1-Jan-1990
          • (1989)A Testability Strategy for Microprocessor ArchitectureIEEE Design & Test10.1109/54.191326:2(18-34)Online publication date: 1-Mar-1989

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