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Area and delay mapping for table-look-up based field programmable gate arrays

Authors:

P. Sawkar,

D. ThomasAuthors Info & Claims

DAC '92: Proceedings of the 29th ACM/IEEE Design Automation Conference

Pages 368 - 373

Published: 01 July 1992 Publication History

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References

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D. Filo, J. C. Yang, F. Mailhot, G. D.Micheli, "Technology Mapping for a Two-Output RAM- based FPGAs" EDA C, February 1991.

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Cited By

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Li HMak WKatkoori SYasuura H(2003)Efficient LUT-based FPGA technology mapping for power minimizationProceedings of the 2003 Asia and South Pacific Design Automation Conference10.1145/1119772.1119842(353-358)Online publication date: 21-Jan-2003
https://dl.acm.org/doi/10.1145/1119772.1119842
Pan PLin CCong JKaptanoglu S(1998)A new retiming-based technology mapping algorithm for LUT-based FPGAsProceedings of the 1998 ACM/SIGDA sixth international symposium on Field programmable gate arrays10.1145/275107.275118(35-42)Online publication date: 1-Mar-1998
https://dl.acm.org/doi/10.1145/275107.275118
Pan PLiu CPennino TYoffa E(1996)Optimal clock period FPGA technology mapping for sequential circuitsProceedings of the 33rd annual Design Automation Conference10.1145/240518.240655(720-725)Online publication date: 1-Jun-1996
https://dl.acm.org/doi/10.1145/240518.240655
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Index Terms

Area and delay mapping for table-look-up based field programmable gate arrays
1. Applied computing
  1. Arts and humanities
    1. Architecture (buildings)
      1. Computer-aided design
  2. Physical sciences and engineering
    1. Engineering
      1. Computer-aided design
2. Hardware

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Information & Contributors

Information

Published In

DAC '92: Proceedings of the 29th ACM/IEEE Design Automation Conference

July 1992

752 pages

ISBN:089791516X

Chairman:
Daniel G. Schweikert
Cadence Design Systems, Inc., San Jose, CA

Publisher

IEEE Computer Society Press

Washington, DC, United States

Publication History

Published: 01 July 1992

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Conference

DAC92

Sponsor:

EDAC
SIGDA
IEEE-CAS
IEEE-CS

DAC92: The 29th ACM/IEEE-CS Design Automation Conference

June 8 - 12, 1992

California, Anaheim, USA

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Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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DAC '25

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62nd ACM/IEEE Design Automation Conference

June 22 - 26, 2025

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Cited By

View all

Li HMak WKatkoori SYasuura H(2003)Efficient LUT-based FPGA technology mapping for power minimizationProceedings of the 2003 Asia and South Pacific Design Automation Conference10.1145/1119772.1119842(353-358)Online publication date: 21-Jan-2003
https://dl.acm.org/doi/10.1145/1119772.1119842
Pan PLin CCong JKaptanoglu S(1998)A new retiming-based technology mapping algorithm for LUT-based FPGAsProceedings of the 1998 ACM/SIGDA sixth international symposium on Field programmable gate arrays10.1145/275107.275118(35-42)Online publication date: 1-Mar-1998
https://dl.acm.org/doi/10.1145/275107.275118
Pan PLiu CPennino TYoffa E(1996)Optimal clock period FPGA technology mapping for sequential circuitsProceedings of the 33rd annual Design Automation Conference10.1145/240518.240655(720-725)Online publication date: 1-Jun-1996
https://dl.acm.org/doi/10.1145/240518.240655
Sawkar PThomas DDunlop A(1993)Performance directed technology mapping for look-up table based FPGAsProceedings of the 30th international Design Automation Conference10.1145/157485.164672(208-212)Online publication date: 1-Jul-1993
https://dl.acm.org/doi/10.1145/157485.164672
Cong JDing YTrevillyan LLightner M(1992)An optimal technology mapping algorithm for delay optimization in lookup-table based FPGA designsProceedings of the 1992 IEEE/ACM international conference on Computer-aided design10.5555/304032.304055(48-53)Online publication date: 8-Nov-1992
https://dl.acm.org/doi/10.5555/304032.304055
Francis RTrevillyan LLightner M(1992)A tutorial on logic synthesis for lookup-table based FPGAsProceedings of the 1992 IEEE/ACM international conference on Computer-aided design10.5555/304032.304053(40-47)Online publication date: 8-Nov-1992
https://dl.acm.org/doi/10.5555/304032.304053

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