[go: up one dir, main page]
More Web Proxy on the site http://driver.im/ skip to main content
10.5555/1870926.1871139acmconferencesArticle/Chapter ViewAbstractPublication PagesdateConference Proceedingsconference-collections
research-article

Parallel X-fault simulation with critical path tracing technique

Published: 08 March 2010 Publication History

Abstract

In this paper, a new very fast fault simulation method to handle the X-fault model is proposed. The method is based on a two-phase procedure. In the first phase, a parallel exact critical path fault tracing is used to determine all the detected stuck-at faults in the circuit, and in the second phase a postprocess is launched which will determine the detectability of X-faults.

References

[1]
L.-T.Wang, Ch.-W. Wu, X. Wen, "VLSI Test Principles and Architectures. Design for Testability," Elsewier, 2006.
[2]
U. Mahlstedt, J. Alt, I. Hollenbeck, "Deterministic Test Generation for Non-Classical Faults on Gate Level," 4th ATS, 1995, pp. 244--251.
[3]
S. Holst, H.-J.Wunderlich, "Adaptive Debug and Diagnosis Without Fault Dictionaries," 13th ETS, 2008, pp. 199--204.
[4]
K. N. Dwarakanath, R. D. Blanton, "Universal Fault Simulation using fault tuples," DAC, Los Angeles, June 2000, pp. 786--789.
[5]
K. B. Keller, "Hierarchical Pattern Faults for Describing Logic Circuit Failure Mechanisms," US Patent 5546408, Aug. 13, 1994.
[6]
R. D. Blanton, J. P. Hayes, "On the Properties of the Input Pattern Fault Model," ACM Trans. Design Automation of Electronic Systems, Vol. 8, No. 1, pp. 108--124, Jan. 2003.
[7]
R. Ubar, "Fault Diagnosis in Cominational Circuits by Solving Boolean Differential Equations," Automatics & Telemechanics, No. 11, 1979, Moscow, pp. 170--183 (in Russian). Transl. in: "Detection of Suspected Faults in Combinational Circuits by Solving Boolean Differential Equations," Automation and Remote Control, Vol. 40, No 11, part 2, Nov. 1980, Plenum Publishing Corporation, USA, pp. 1693--1703.
[8]
Y. Cho, S. Mitra, E. J. McCluskey, "Gate Exhaustive Testing," International Test Conference, 2005.
[9]
A. Jas, S. Natarajan, S. Patil, "The Region-Exhaustive Fault Model," 16th Asian Test Symp. Beijing, China, Oct. 2007, pp. 13--18.
[10]
J. M. Acken, S. D. Millman, "Accurate Modeling and Simulating of Bridge Faults," Custom Integrated Circuits Conf., San Diego, CA, May 1991, pp. 17.4.1--17.4.4.
[11]
P. Maxwell, R. Aiken, "Biased Voting: A Method for Simulating CMOS Bridging Faults in the Presence of Variable Gate Logic Thresholds," Proc. International Test Conference, 1993, pp. 63--72.
[12]
L. Zhuo, X. Lu, W. Qiu, W. Shi, D. M. H. Walker, "A Circuit Level Fault Model for Resistive Opens and Bridges," Proc. VLSI Test Symposium, Napa, CA, Apr./May 2003, pp. 379--384.
[13]
P. Engelke, I. Polian, M. Renovell, "B.Becker. Simulating resistive bridging and stuck-at faults," IEEE Trans. on CAD of IC and Systems, Vol. 25, No. 10, pp. 2181--2192, Oct. 2006.
[14]
A. Rousset, A. Bosio, P. Girard, C. Landrault, S. Pravossoudovitch, A. Virazel, "Fast Bridging Fault Diagnosis Using Logic Information," 16th ATS. Beijing, China, Oct. 2007, pp. 33--38.
[15]
S. K. Jain, V. D. Agrawal, "Modeling and Test Generation Algorithms for MOS Circuits," IEEE Trans. Comput., Vol. C-34, No. 5, pp. 426--433, May 1985.
[16]
H. K. Lee, D. S. Ha, "SOPRANO: An Efficent Automatic Test Pattern Generator for Stuck-Open Faults in CMOS Combinational Circuits," DAC, Orlando, FL, June 1990, pp. 660--666.
[17]
A. Kristic, K. T. Cheng, "Delay Fault Testing for VLSI Circuits," Dordrecht, The Netherlands, Kluwer Academic Publishers, Oct. 1998.
[18]
G. Chen, S. Reddy, I. Pomeranz, J. Rajski, P. Engelke, B. Becker, "A Unified Fault Model and Test Generation Procedure for Interconnect Opens and Bridges," 10th ETS, Tallinn, May 2005.
[19]
D. Lavo, T. Larrabee, B. Chess, "Beyond the Byzantine Generals: Unexpected Behavior and Bridging Fault Diagnosis," Proc. International Test Conference, 1996, pp. 611--619.
[20]
S. Huang, "Speeding up the Byzantine Fault Diagnosis Using Symbolic Simulation," Proc. VTS, 2002, pp. 193--198.
[21]
Y. Yamato, Y. Nakamura, K. Miyase, X. Wen, S. Kajihara, "A Novel PerTest Fault Diagnosis Method Based on the Extended X-Fault Model for Deep-Submicron LSI Circuits," IEICE Trans. Inf. & Syst., Vol. E-91-D, No. 3 March 2008, pp. 667--674.
[22]
X. Wen, T. Miyoshi, S. Kajihara, L.-T. Wang, K. Saluja, K. Kinoshita, "On Per-Test Fault Diagnosis Using the X-Fault Model," ICCAD, Nov. 2004, pp. 633--640.
[23]
I. Polian, Y. Nakamura, P. Engelke, S. Spinner, K. Miyase, S. Kajihara, B. Becker, X. Wen, "Diagnosios of Realistic Defects Based on the X-Fault Model," DDECS, April 2008, pp. 1--5.
[24]
J. A. Waicukauski, et al., "Fault Simulation of Structured VLSI," VLSI Systems Design, Vol. 6, No. 12, pp. 20--32, 1985.
[25]
M. Abramovici, P. R. Menon, D. T. Miller, "Critical Path Tracing - Alternative to Fault Simulation,". DAC, pp. 2--5, 1987
[26]
K. J. Antreich, M. H. Schulz, "Accelerated Fault Simulation and fault grading in combinational circuits", IEEE Trans. on CAD, Vol. 6, No. 5, pp. 704--712, 1987.
[27]
F. Maamari, J. Rajski, "A method of fault simulation based on stem region," IEEE Trans. CAD, Vol. 9, No. 2, pp. 212--220, 1990.
[28]
P. Engelke, B. Becker, M. Renovell, J. Schlöffel, B. Braitling, I. Polian, "SUPERB: Simulator Utilizing Parallel Evaluation of Resistive Bridges," ACM Trans. on Design Automation of Electronic Systems, Vol. 14, No. 4, Article 56, 21 p., 2009.
[29]
S. Hillebrecht, I. Polian, P. Engelke, B. Becker, M. Keim, W-T. Cheng, "Extraction, Simulation and Test Generation for Interconnect Open Defects Based on Enhanced Aggressor-Victim Model," International Test Conference, Papers 33.3, 10 p., 2008.
[30]
D. B. Armstrong, "A deductive method for simulating faults in circuits," IEEE Trans. Comp., C-21(5), 464--471, 1972.
[31]
E. G. Ulrich, T. Baker, "Concurrent simulator of nearly identical digital networks," IEEE Trans. on Comp., 7(4), pp. 39--44, 1974.
[32]
W. T. Cheng, M. L. Yu, "Differential fault simulation: a fast method using minimal memory," DAC, pp. 424--428, 1989.
[33]
P. Goel, "Test Generation Cost Analysis and Projections", Proc. DAC, pp. 77--84, 1980.
[34]
L. Wu, D. M. H. Walker, "A Fast Algorithm for Critical Path Tracing in VLSI," Int. Symposium on Defect and Fault Tolerance in VLSI Systems, Oct. 2005, pp. 178--186.
[35]
R. Ubar, S. Devadze, J. Raik, A. Jutman, "Ultra Fast Parallel Fault Analysis on Structural BDDs," ETS, Freiburg, May 20--24, 2007.
[36]
R. Ubar, S. Devadze, J. Raik, A Jutman, "Parallel Fault Backtracing for Calculation of Fault Coverage," 13th ASPDAC, Seoul, Korea, 2008, pp. 667--672.
[37]
A. Thayse, "Boolean Calculus of Differences," Springer Verlag, 1981.
[38]
H. K. Lee, D. S. Ha, "An efficient, forward fault simulation algorithm based on the parallel pattern single fault propagation," Proc. International Test Conference, pp. 946--955, 1991

Cited By

View all
  • (2015)Fault simulation with parallel exact critical path tracing in multiple core environmentProceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition10.5555/2755753.2757085(1180-1185)Online publication date: 9-Mar-2015
  • (2015)A Framework for Combining Concurrent Checking and On-Line Embedded Test for Low-Latency Fault Detection in NoC RoutersProceedings of the 9th International Symposium on Networks-on-Chip10.1145/2786572.2788713(1-8)Online publication date: 28-Sep-2015
  • (2015)Transition delay fault simulation with parallel critical path back-tracing and 7-valued algebraMicroprocessors & Microsystems10.1016/j.micpro.2015.05.00339:8(1130-1138)Online publication date: 1-Nov-2015
  • Show More Cited By

Recommendations

Comments

Please enable JavaScript to view thecomments powered by Disqus.

Information & Contributors

Information

Published In

cover image ACM Conferences
DATE '10: Proceedings of the Conference on Design, Automation and Test in Europe
March 2010
1868 pages
ISBN:9783981080162

Sponsors

  • EDAA: European Design Automation Association
  • ECSI
  • EDAC: Electronic Design Automation Consortium
  • SIGDA: ACM Special Interest Group on Design Automation
  • The IEEE Computer Society TTTC
  • The IEEE Computer Society DATC
  • The Russian Academy of Sciences: The Russian Academy of Sciences

Publisher

European Design and Automation Association

Leuven, Belgium

Publication History

Published: 08 March 2010

Check for updates

Author Tags

  1. X-fault model
  2. digital circuits
  3. fault simulation
  4. parallel exact critical path fault tracing

Qualifiers

  • Research-article

Conference

DATE '10
Sponsor:
  • EDAA
  • EDAC
  • SIGDA
  • The Russian Academy of Sciences
DATE '10: Design, Automation and Test in Europe
March 8 - 12, 2010
Germany, Dresden

Acceptance Rates

Overall Acceptance Rate 518 of 1,794 submissions, 29%

Upcoming Conference

DATE '25
Design, Automation and Test in Europe
March 31 - April 2, 2025
Lyon , France

Contributors

Other Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

  • Downloads (Last 12 months)1
  • Downloads (Last 6 weeks)0
Reflects downloads up to 21 Jan 2025

Other Metrics

Citations

Cited By

View all
  • (2015)Fault simulation with parallel exact critical path tracing in multiple core environmentProceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition10.5555/2755753.2757085(1180-1185)Online publication date: 9-Mar-2015
  • (2015)A Framework for Combining Concurrent Checking and On-Line Embedded Test for Low-Latency Fault Detection in NoC RoutersProceedings of the 9th International Symposium on Networks-on-Chip10.1145/2786572.2788713(1-8)Online publication date: 28-Sep-2015
  • (2015)Transition delay fault simulation with parallel critical path back-tracing and 7-valued algebraMicroprocessors & Microsystems10.1016/j.micpro.2015.05.00339:8(1130-1138)Online publication date: 1-Nov-2015
  • (2015)Functional self-test of high-performance pipe-lined signal processing architecturesMicroprocessors & Microsystems10.1016/j.micpro.2014.11.00239:8(909-918)Online publication date: 1-Nov-2015
  • (2011)Finding the description of structure by counting methodProceedings of the 37th international conference on Current trends in theory and practice of computer science10.5555/1946370.1946408(455-466)Online publication date: 22-Jan-2011

View Options

Login options

View options

PDF

View or Download as a PDF file.

PDF

eReader

View online with eReader.

eReader

Media

Figures

Other

Tables

Share

Share

Share this Publication link

Share on social media