A fast algorithm for critical path tracing in VLSI digital circuits
L Wu, DMH Walker - … on Defect and Fault Tolerance in VLSI …, 2005 - ieeexplore.ieee.org
L Wu, DMH Walker
20th IEEE International Symposium on Defect and Fault Tolerance in …, 2005•ieeexplore.ieee.orgAn exact, linear-time critical path tracing algorithm is presented. The performance of critical
path tracing is determined primarily by the efficiency of stem analysis. The proposed strategy
can determine stem criticality in one pass based on six rules. Experiments on ISCAS85 and
ISCAS89 benchmark circuits show that the computation time is nearly linear in the number of
nets.
path tracing is determined primarily by the efficiency of stem analysis. The proposed strategy
can determine stem criticality in one pass based on six rules. Experiments on ISCAS85 and
ISCAS89 benchmark circuits show that the computation time is nearly linear in the number of
nets.
An exact, linear-time critical path tracing algorithm is presented. The performance of critical path tracing is determined primarily by the efficiency of stem analysis. The proposed strategy can determine stem criticality in one pass based on six rules. Experiments on ISCAS85 and ISCAS89 benchmark circuits show that the computation time is nearly linear in the number of nets.
ieeexplore.ieee.org