Article

A Fast Algorithm for Critical Path Tracing in VLSI Digital Circuits

Authors:

Lei Wu,

D. M. H. WalkerAuthors Info & Claims

DFT '05: Proceedings of the 20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems

Pages 178 - 186

https://doi.org/10.1109/DFTVS.2005.6

Published: 03 October 2005 Publication History

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Abstract

An exact, linear-time critical path tracing algorithm is presented. The performance of critical path tracing is determined primarily by the efficiency of stem analysis. The proposed strategy can determine stem criticality in one pass based on six rules. Experiments on ISCAS85 and ISCAS89 benchmark circuits show that the computation time is nearly linear in the number of nets.

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Gorev MUbar RDevadze SNebel WAtienza D(2015)Fault simulation with parallel exact critical path tracing in multiple core environmentProceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition10.5555/2755753.2757085(1180-1185)Online publication date: 9-Mar-2015
https://dl.acm.org/doi/10.5555/2755753.2757085
Kõusaar JUbar RDevadze SRaik J(2015)Transition delay fault simulation with parallel critical path back-tracing and 7-valued algebraMicroprocessors & Microsystems10.1016/j.micpro.2015.05.00339:8(1130-1138)Online publication date: 1-Nov-2015
https://dl.acm.org/doi/10.1016/j.micpro.2015.05.003
Ubar RDevadze SRaik JJutman ADe Micheli GAl-Hashimi BMueller WMacii E(2010)Parallel X-fault simulation with critical path tracing techniqueProceedings of the Conference on Design, Automation and Test in Europe10.5555/1870926.1871139(879-884)Online publication date: 8-Mar-2010
https://dl.acm.org/doi/10.5555/1870926.1871139
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A Fast Algorithm for Critical Path Tracing in VLSI Digital Circuits
1. Hardware

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DFT '05: Proceedings of the 20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems

October 2005

598 pages

ISBN:0769524648

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IEEE Computer Society

United States

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Published: 03 October 2005

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Gorev MUbar RDevadze SNebel WAtienza D(2015)Fault simulation with parallel exact critical path tracing in multiple core environmentProceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition10.5555/2755753.2757085(1180-1185)Online publication date: 9-Mar-2015
https://dl.acm.org/doi/10.5555/2755753.2757085
Kõusaar JUbar RDevadze SRaik J(2015)Transition delay fault simulation with parallel critical path back-tracing and 7-valued algebraMicroprocessors & Microsystems10.1016/j.micpro.2015.05.00339:8(1130-1138)Online publication date: 1-Nov-2015
https://dl.acm.org/doi/10.1016/j.micpro.2015.05.003
Ubar RDevadze SRaik JJutman ADe Micheli GAl-Hashimi BMueller WMacii E(2010)Parallel X-fault simulation with critical path tracing techniqueProceedings of the Conference on Design, Automation and Test in Europe10.5555/1870926.1871139(879-884)Online publication date: 8-Mar-2010
https://dl.acm.org/doi/10.5555/1870926.1871139
Ubar RDevadze SRaik JJutman AKyung CChoi KHa S(2008)Parallel fault backtracing for calculation of fault coverageProceedings of the 2008 Asia and South Pacific Design Automation Conference10.5555/1356802.1356964(667-672)Online publication date: 21-Jan-2008
https://dl.acm.org/doi/10.5555/1356802.1356964

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Parallel critical path tracing—A fault simulation algorithm for combinational circuits

An Efficient Critical Path Tracing Algorithm for Designing HighPerformance Vlsi Systems

Fast algorithms for retiming large digital circuits

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