ISCA

A multi-instruction-multi-data stream computer architecture is presented which is aimed at supporting highly concurrent general-purpose computation. The proposed machine is organised as a set of autonomous resources, each having direct access to a ...

This paper presents a class of algorithms, On-Line Continued Sums/Products, which are amenable for the efficient implementation by a pipeline architecture. The implementation of these algorithms provides a simple and fast method for the evaluation of ...

Some protection mechanisms support the implementation of abstract type objects. The “separation of privilege” and the “least privilege” principles define several requirements that must guide the design of such protection mechanisms. Some of these ...

This paper deals with an automatic recovery mechanism designed to prevent the occurrence of subtract errors at the computer architecture level. This mechanism always detects the occurence of subtract errors whenever addition or subtraction is performed. ...

ARCADE is a research project in computer architecture. We first discuss its motivations and goals, wich are primarily the design of a dynamically adaptive system, and the use of performance evaluation methods as a design tool. The resulting system is ...

Register allocation schemes are presented that effectively use many registers in the execution of block-structured languages. Simulation statistics for a machine with many registers and a conventional architecture are compared. The results indicate that ...

Presented is the design of a flexible expandable multi-processor system for video graphics and image processing. The design involves a central controller which broadcasts data to a variable number of independently executing processing units, each of ...

This paper describes an array processor designed for signal processing in radar applications. The processor consists of a large number of microprocessor-based processing elements and is designed to be adaptive in real-time processing requirements. The ...

Cache storage is a proven memory speedup technique in large mainframe computers. Two of the main difficulties associated with the use of this concept in small machines are the high relative cost and complexity of the cache controller. An LSI bit-slice ...

The paper describes the results of simulation experiments of a tree organized multicomputer now being constructed in the Department of Computer Science at Stony Brook.

First the structure of the multicomputer is introduced. This is based on, (i) ...

X-NODE is a single-chip VLSI processor to be realized in the mid 1980's and to be used as a building block for a tree-structured multiprocessor system (X-TREE). Three major trends influence the design of this processor: the continuing evolution of VLSI ...

Functional aspects of a machine called FLATS are described. FLATS aims to efficiently run both numerical and algebraic programs. Overflow free and variable precision arithmetic, table look-up computation, and associative computation based on single-hit ...

This paper presents a simplified approach to developing performance models for complex systems, such as distributed processing systems, and illustrates the approach by applying it to studying the performance of a new ring-structured microcomputer ...

In this paper, a comparison of the performance of optimally designed computer systems with and without virtual memory is made. The computer systems in question are modeled by closed queuing networks of the central server type. The design of the systems ...

As CPUs have become larger and more complex, it has become increasingly more difficult during hardware design and implementation to predict how well a CPU will perform. Furthermore, buyers of such machines have a similar problem in evaluating CPU ...

Microprogramming is a basic technique that realizes functionally specialized processors in a functionally distributed multiprocessor system which consists of many small processors. In such a multiprocessor system, it is necessary to change processor ...

This paper presents an overview of the architecture of the SPERRY UNIVAC® 1100 Series systems. The principal topics are instruction and data formats, main storage and addressing, process management, and I/O.

This paper presents low-level architectural features for supporting software systems which are organized as collections of concurrent processes in which processes may be created or destroyed and interprocess interaction paths may be established and ...

This paper presents a formal scheme for addressing base and apex nodes in SW-banyan networks. This scheme is used for routing packets in the network. Packet-switching, in conjunction with the the circuit-switch mode of operation, offers a very flexible ...

A new class of interconnection networks is proposed for processor to memory communication in multiprocessing systems. These networks allow a direct link between any processor to any memory module. The cost of these networks is considerably less than ...

This paper proves that, given a reliable time-bounded arbiter, it is possible to realize a reliable (i.e. runt-free) inertial delay, and vice-versa. It therefore shows that the time-bounded arbiter and the inertial delay are equally realizable. ...

The design of a modular crossbar network that can be used to support a multiprocessor is reviewed in this paper. The network is viewed at a functional level and the objectives, motivations and resultant design decisions are discussed. Two of these ...

The Experimental Polyprocessor System (EPOS) is described. It is a new computer system based on the concept of the polyprocessor and is intended to obtain a high degree of extensibility, cost/performance, adaptability and reliability. EPOS is composed ...

EPOS's operating system structure, firmware structure, functional distribution, and restructuring are described. EPOS processors are functionally specialized to user functions as well as operating system functions. The performance improvement by ...

This paper describes an asynchronous circuit switching network for multiple-processor systems. Several circuit switching networks for various applications have been proposed and constructed. However, there are problems associated with these networks. ...

The automatic coordination of instruction execution of SISD processors is examined in the context of minimizing the effects of branch execution. Three areas, instruction prefetch, branch resolution, and issuer organization are examined for possible ...

The emulator network, a single stage interconnection network, can be used to simulate a wide variety of single stage and multistage SIMD interconnection networks. These include the STARAN, the omega, the data manipulator, and the Illiac networks. A ...