Article

Free access

Processor-memory interconnections for multiprocessors

Author:

Janak H. PatelAuthors Info & Claims

ISCA '79: Proceedings of the 6th annual symposium on Computer architecture

Pages 168 - 177

https://doi.org/10.1145/800090.802906

Published: 23 April 1979 Publication History

PDF eReader

Abstract

A new class of interconnection networks is proposed for processor to memory communication in multiprocessing systems. These networks allow a direct link between any processor to any memory module. The cost of these networks is considerably less than that of full crossbars. Moreover, the design and control of these networks is simple. The proposed networks and the full crossbars are analyzed with respect to the bandwidth and the cost.

References

[1]

D. H. Lawrie, "Access and Alignment of Data in an Array Processor", IEEE Trans. Comput., Vol. C-24, pp. 1145-1155, Dec. 1975.

Google Scholar

[2]

M. C. Pease, "The Indirect Binary n-Cube Microprocessor Array", IEEE Trans. Comput., Vol. C-26, pp. 458-473, May 1977.

Google Scholar

[3]

H. J. Siegel and S. D. Smith, "Study of Multistage SIMD Interconnection Networks", Proc. 5th Annual Symp. on Computer Architecture, pp. 223-229, April 1978.

Digital Library

Google Scholar

[4]

H. S. Stone, "Parallel Processing with the Perfect Shuffle", IEEE Trans. Comput., Vol. C-20, pp. 153-161, Feb. 1971.

Google Scholar

[5]

V. E. Benes, Mathematical Theory of Connecting Networks and Telephone Traffic, Academic Press, New York, 1965.

Google Scholar

[6]

D. Y. Chang, D. J. Kuck and D. H. Lawrie, "On the Effective Bandwidth of Parallel Memories", IEEE Trans. Comput., Vol. C-26, pp. 480-490, May 1977.

Google Scholar

Cited By

View all

(2016)Virtualized I/OAttaining High Performance Communications10.1201/b10249-17(261-282)Online publication date: 19-Apr-2016
https://doi.org/10.1201/b10249-17
Gomes AAlves FFerreira RNacif Jde Lima RCunha APlett Cde Oliveira W(2015)Increasing Observability in Post-Silicon Debug Using Asymmetric Omega NetworksProceedings of the 28th Symposium on Integrated Circuits and Systems Design10.1145/2800986.2801011(1-7)Online publication date: 31-Aug-2015
https://dl.acm.org/doi/10.1145/2800986.2801011
Rajkumar SGoyal N(2014)Design of 4-disjoint gamma interconnection network layouts and reliability analysis of gamma interconnection NetworksThe Journal of Supercomputing10.1007/s11227-014-1175-069:1(468-491)Online publication date: 1-Jul-2014
https://dl.acm.org/doi/10.1007/s11227-014-1175-0
Show More Cited By

Index Terms

Processor-memory interconnections for multiprocessors

Recommendations

Performance of Processor-Memory Interconnections for Multiprocessors

A class of interconnection networks based on some existing permutation networks is described with applications to processor to memory communication in multiprocessing systems. These networks, termed delta networks, allow a direct link between any ...
Processor Allocation Problem for NoC-Based Chip Multiprocessors
ITNG '09: Proceedings of the 2009 Sixth International Conference on Information Technology: New Generations

Chip multiprocessors (CMPs) have become the primary approach to build high-performance microprocessors. Such systems require fast and efficient communication that can only be realized using Network on Chip (NoC), particularly for large systems. ...
An Analysis of Processor-Memory Interconnection Networks

An interference analysis of the interconnection networks (IN's) for tightly coupled multiprocessors is presented in this correspondence. The interconnections considered are crossbars and delta networks. Two situations are examined: when a memory module ...

Comments

Please enable JavaScript to view thecomments powered by Disqus.

Information & Contributors

Information

Published In

ISCA '79: Proceedings of the 6th annual symposium on Computer architecture

April 1979

246 pages

ISBN:9781450373975

DOI:10.1145/800090

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 23 April 1979

Permissions

Request permissions for this article.

Request Permissions

Check for updates

Qualifiers

Article

Acceptance Rates

Overall Acceptance Rate 543 of 3,203 submissions, 17%

Upcoming Conference

ISCA '25

Sponsor:
sigarch

The 52nd Annual International Symposium on Computer Architecture

June 21 - 25, 2025

Tokyo , Japan

Contributors

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

93
Total Citations
View Citations
665
Total Downloads

Downloads (Last 12 months)77
Downloads (Last 6 weeks)9

Reflects downloads up to 28 Jan 2025

Other Metrics

View Author Metrics

Citations

Cited By

View all

(2016)Virtualized I/OAttaining High Performance Communications10.1201/b10249-17(261-282)Online publication date: 19-Apr-2016
https://doi.org/10.1201/b10249-17
Gomes AAlves FFerreira RNacif Jde Lima RCunha APlett Cde Oliveira W(2015)Increasing Observability in Post-Silicon Debug Using Asymmetric Omega NetworksProceedings of the 28th Symposium on Integrated Circuits and Systems Design10.1145/2800986.2801011(1-7)Online publication date: 31-Aug-2015
https://dl.acm.org/doi/10.1145/2800986.2801011
Rajkumar SGoyal N(2014)Design of 4-disjoint gamma interconnection network layouts and reliability analysis of gamma interconnection NetworksThe Journal of Supercomputing10.1007/s11227-014-1175-069:1(468-491)Online publication date: 1-Jul-2014
https://dl.acm.org/doi/10.1007/s11227-014-1175-0
Vasiliadis DRizos GVassilakis C(2013)Modelling and performance study of finite-buffered blocking multistage interconnection networks supporting natively 2-class priority routing trafficJournal of Network and Computer Applications10.1016/j.jnca.2012.12.01636:2(723-737)Online publication date: 1-Mar-2013
https://dl.acm.org/doi/10.1016/j.jnca.2012.12.016
Rezazadeh MSafaei FMoaiyeri M(2011)Comparative Performance Study of Multi-stage Interconnection Networks Using Carbon Nanotube SwitchesProceedings of the 2011 IFIP 9th International Conference on Embedded and Ubiquitous Computing10.1109/EUC.2011.24(326-331)Online publication date: 24-Oct-2011
https://dl.acm.org/doi/10.1109/EUC.2011.24
Tehrani MSafaei FMoaiyeri MNavi K(2011)Design and implementation of Multistage Interconnection Networks using Quantum-dot Cellular AutomataMicroelectronics Journal10.1016/j.mejo.2011.03.00442:6(913-922)Online publication date: 1-Jun-2011
https://dl.acm.org/doi/10.1016/j.mejo.2011.03.004
Vasiliadis DRizos GVassilakis C(2010)Performance study of multilayered multistage interconnection networks under hotspot traffic conditionsJournal of Computer Systems, Networks, and Communications10.1155/2010/4030562010(1-11)Online publication date: 1-Jan-2010
https://dl.acm.org/doi/10.1155/2010/403056
Vasiliadis DRizos GVassilakis CGlavas E(2009)Performance Evaluation of Multicast Routing over Multilayer Multistage Interconnection NetworksProceedings of the 2009 Fifth Advanced International Conference on Telecommunications10.1109/AICT.2009.72(395-403)Online publication date: 24-May-2009
https://dl.acm.org/doi/10.1109/AICT.2009.72
Vasiliadis DRizos GVassilakis C(2009)Routing and Performance Evaluation of Dual Priority Delta Networks under Hotspot EnvironmentProceedings of the 2009 First International Conference on Advances in Future Internet10.1109/AFIN.2009.12(24-30)Online publication date: 18-Jun-2009
https://dl.acm.org/doi/10.1109/AFIN.2009.12
Vasiliadis DRizos GVassilakis CGlavas E(2008)Routing and Performance Analysis of Double-Buffered Omega Networks Supporting Multi-class Priority TrafficProceedings of the 2008 Third International Conference on Systems and Networks Communications10.1109/ICSNC.2008.10(56-63)Online publication date: 26-Oct-2008
https://dl.acm.org/doi/10.1109/ICSNC.2008.10
Show More Cited By

View Options

View options

PDF

View or Download as a PDF file.

PDF

eReader

View online with eReader.

eReader

Login options

Check if you have access through your login credentials or your institution to get full access on this article.

Cited By

Index Terms

Recommendations

Performance of Processor-Memory Interconnections for Multiprocessors

Processor Allocation Problem for NoC-Based Chip Multiprocessors

An Analysis of Processor-Memory Interconnection Networks