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Power reduction by simultaneous voltage scaling and gate sizing

Authors:

Chunhong Chen,

Majid SarrafzadehAuthors Info & Claims

ASP-DAC '00: Proceedings of the 2000 Asia and South Pacific Design Automation Conference

Pages 333 - 338

https://doi.org/10.1145/368434.368668

Published: 28 January 2000 Publication History

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Cited By

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Ghiasi S(2005)Efficient Implementation Selection via Time Budgeting Complexity Analysis and Leakage Optimization Case StudyProceedings of the 2005 International Conference on Computer Design10.1109/ICCD.2005.44(127-129)Online publication date: 2-Oct-2005
https://dl.acm.org/doi/10.1109/ICCD.2005.44
Mukherjee ASankaranarayan R(2004)Retiming and clock scheduling to minimize simultaneous switchingIEEE International SOC Conference, 2004. Proceedings.10.1109/SOCC.2004.1362427(259-262)Online publication date: 2004
https://doi.org/10.1109/SOCC.2004.1362427
Murugavel ARanganathan N(2004)Gate sizing and buffer insertion using economic models for power optimization17th International Conference on VLSI Design. Proceedings.10.1109/ICVD.2004.1260924(195-200)Online publication date: 2004
https://doi.org/10.1109/ICVD.2004.1260924
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Published In

ASP-DAC '00: Proceedings of the 2000 Asia and South Pacific Design Automation Conference

January 2000

691 pages

ISBN:0780359747

DOI:10.1145/368434

Chairman:
Kenji Yoshida
Toshiba Corp., Kawasaki, Japan

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Publication History

Published: 28 January 2000

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ASP-DAC00: Asia and South Pacific Design Automation Conference 2000

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Overall Acceptance Rate 466 of 1,454 submissions, 32%

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Cited By

View all

Ghiasi S(2005)Efficient Implementation Selection via Time Budgeting Complexity Analysis and Leakage Optimization Case StudyProceedings of the 2005 International Conference on Computer Design10.1109/ICCD.2005.44(127-129)Online publication date: 2-Oct-2005
https://dl.acm.org/doi/10.1109/ICCD.2005.44
Mukherjee ASankaranarayan R(2004)Retiming and clock scheduling to minimize simultaneous switchingIEEE International SOC Conference, 2004. Proceedings.10.1109/SOCC.2004.1362427(259-262)Online publication date: 2004
https://doi.org/10.1109/SOCC.2004.1362427
Murugavel ARanganathan N(2004)Gate sizing and buffer insertion using economic models for power optimization17th International Conference on VLSI Design. Proceedings.10.1109/ICVD.2004.1260924(195-200)Online publication date: 2004
https://doi.org/10.1109/ICVD.2004.1260924
Chen CSapatnekar SPedram M(2002)Physical design with multiple on-chip voltagesProceedings of the 2002 international symposium on Physical design10.1145/505388.505417(118-118)Online publication date: 7-Apr-2002
https://dl.acm.org/doi/10.1145/505388.505417
Chunhong Chen Sarrafzadeh M(2002)Simultaneous voltage scaling and gate sizing for low-power designIEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing10.1109/TCSII.2002.80296449:6(400-408)Online publication date: Jun-2002
https://doi.org/10.1109/TCSII.2002.802964
Mahnke TPanenka SEmbacher MStechele WHoeld W(2002)Efficiency of dual supply voltage logic synthesis for low power in consideration of varying delay constraint strictness9th International Conference on Electronics, Circuits and Systems10.1109/ICECS.2002.1046265(701-704)Online publication date: 2002
https://doi.org/10.1109/ICECS.2002.1046265
Mahnke TStechele WEmbacher MHoeld W(2002)Impact of technology evolution on dual supply voltage scaling and gate resizing in power-driven logic synthesis9th International Conference on Electronics, Circuits and Systems10.1109/ICECS.2002.1046264(697-700)Online publication date: 2002
https://doi.org/10.1109/ICECS.2002.1046264
Zhang YHu XChen D(2002)Cell selection from technology libraries for minimizing powerIntegration10.1016/S0167-9260(02)00022-631:2(133-158)Online publication date: May-2002
https://doi.org/10.1016/S0167-9260(02)00022-6
Zhang YHu XChen DGoto S(2001)Cell selection from technology libraries for minimizing powerProceedings of the 2001 Asia and South Pacific Design Automation Conference10.1145/370155.370562(609-614)Online publication date: 30-Jan-2001
https://dl.acm.org/doi/10.1145/370155.370562
Chen CSrivastava ASarrafzadeh M(2001)On gate level power optimization using dual-supply voltagesIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/92.9534969:5(616-629)Online publication date: 1-Oct-2001
https://dl.acm.org/doi/10.1109/92.953496
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