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Reconfigurable computing: its concept and a practical embodiment using newly developed dynamically reconfigurable logic (DRL) LSI: invited talk

Authors:

Masakazu Yamashina,

Masato MotomuraAuthors Info & Claims

ASP-DAC '00: Proceedings of the 2000 Asia and South Pacific Design Automation Conference

Pages 329 - 332

https://doi.org/10.1145/368434.368666

Published: 28 January 2000 Publication History

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Wattebled PDiguet JDekeyser J(2012)Membrane-based design and management methodology for parallel dynamically reconfigurable embedded systems7th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC)10.1109/ReCoSoC.2012.6322884(1-8)Online publication date: Jul-2012
https://doi.org/10.1109/ReCoSoC.2012.6322884
Zhang WJha NShang L(2010)Low-power 3D nano/CMOS hybrid dynamically reconfigurable architectureACM Journal on Emerging Technologies in Computing Systems10.1145/1777401.17774036:3(1-32)Online publication date: 13-Aug-2010
https://dl.acm.org/doi/10.1145/1777401.1777403
WAIDYASOORIYA HHARIYAMA MKAMEYAMA M(2009)Implementation of a Partially Reconfigurable Multi-Context FPGA Based on Asynchronous ArchitectureIEICE Transactions on Electronics10.1587/transele.E92.C.539E92-C:4(539-549)Online publication date: 2009
https://doi.org/10.1587/transele.E92.C.539
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Published In

ASP-DAC '00: Proceedings of the 2000 Asia and South Pacific Design Automation Conference

January 2000

691 pages

ISBN:0780359747

DOI:10.1145/368434

Chairman:
Kenji Yoshida
Toshiba Corp., Kawasaki, Japan

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Publication History

Published: 28 January 2000

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ASP-DAC00: Asia and South Pacific Design Automation Conference 2000

Yokohama, Japan

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Overall Acceptance Rate 466 of 1,454 submissions, 32%

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Cited By

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Wattebled PDiguet JDekeyser J(2012)Membrane-based design and management methodology for parallel dynamically reconfigurable embedded systems7th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC)10.1109/ReCoSoC.2012.6322884(1-8)Online publication date: Jul-2012
https://doi.org/10.1109/ReCoSoC.2012.6322884
Zhang WJha NShang L(2010)Low-power 3D nano/CMOS hybrid dynamically reconfigurable architectureACM Journal on Emerging Technologies in Computing Systems10.1145/1777401.17774036:3(1-32)Online publication date: 13-Aug-2010
https://dl.acm.org/doi/10.1145/1777401.1777403
WAIDYASOORIYA HHARIYAMA MKAMEYAMA M(2009)Implementation of a Partially Reconfigurable Multi-Context FPGA Based on Asynchronous ArchitectureIEICE Transactions on Electronics10.1587/transele.E92.C.539E92-C:4(539-549)Online publication date: 2009
https://doi.org/10.1587/transele.E92.C.539
Economakos GXydis S(2008)A Scheduling Postprocessor to Exploit Morphable RTL Components During High-Level SynthesisProceedings of the 2008 11th EUROMICRO Conference on Digital System Design Architectures, Methods and Tools10.1109/DSD.2008.85(494-499)Online publication date: 3-Sep-2008
https://dl.acm.org/doi/10.1109/DSD.2008.85
Economakos G(2006)High-level synthesis with reconfigurable datapath componentsProceedings of the 20th international conference on Parallel and distributed processing10.5555/1898699.1898703(212-212)Online publication date: 25-Apr-2006
https://dl.acm.org/doi/10.5555/1898699.1898703
Economakos G(2006)High-level synthesis with reconfigurable datapath componentsProceedings 20th IEEE International Parallel & Distributed Processing Symposium10.1109/IPDPS.2006.1639477(4 pp.)Online publication date: 2006
https://doi.org/10.1109/IPDPS.2006.1639477
Zhe Zhou Sheqin Dong Xianlong Hong Yu-liang Wu Kajitani Y(2005)A new approach based on LFF for optimization of dynamic hardware reconfigurations2005 IEEE International Symposium on Circuits and Systems10.1109/ISCAS.2005.1464811(1210-1211)Online publication date: 2005
https://doi.org/10.1109/ISCAS.2005.1464811
Sakane HYakay LKarna VLeung CGao G(2003)DIMES: an iterative emulation platform for Multiprocessor-System-On-Chip designsProceedings. 2003 IEEE International Conference on Field-Programmable Technology (FPT) (IEEE Cat. No.03EX798)10.1109/FPT.2003.1275754(244-251)Online publication date: 2003
https://doi.org/10.1109/FPT.2003.1275754
Sekine MKanamaru TKudoh KImanaka HShiga YIto HMyokan Y(2003)Hardware objects of the circuits for roboticsProceedings 2003 IEEE International Symposium on Computational Intelligence in Robotics and Automation. Computational Intelligence in Robotics and Automation for the New Millennium (Cat. No.03EX694)10.1109/CIRA.2003.1222206(1421-1426)Online publication date: 2003
https://doi.org/10.1109/CIRA.2003.1222206
Kaneko NAmano H(2002)A General Hardware Design Model for Multicontext FPGAsProceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications10.5555/647929.740245(1037-1047)Online publication date: 2-Sep-2002
https://dl.acm.org/doi/10.5555/647929.740245
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