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Gabriel H. Loh
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2020 – today
- 2024
- [c95]Alan Smith, Gabriel H. Loh, Michael J. Schulte, Mike Ignatowski, Samuel Naffziger, Mike Mantor, Nathan Kalyanasundharam, Vamsi Alla, Nicholas Malaya, Joseph L. Greathouse, Eric Chapman, Raja Swaminathan:
Realizing the AMD Exascale Heterogeneous Processor Vision : Industry Product. ISCA 2024: 876-889 - [c94]Alan Smith, Gabriel H. Loh, John J. Wuu, Samuel Naffziger, Tyrone Huang, Hugh McIntyre, Ramon Mangaser, Wonjun Jung, Raja Swaminathan:
AMD Instinct™ MI300X Accelerator: Packaging and Architecture Co-Optimization. VLSI Technology and Circuits 2024: 1-2 - 2023
- [c93]Gabriel H. Loh, Raja Swaminathan:
The Next Era for Chiplet Innovation. DATE 2023: 1-6 - [c92]Gabriel H. Loh
, Michael J. Schulte
A Research Retrospective on AMD's Exascale Computing Journey. ISCA 2023: 81:1-81:14 - [c91]Raja Swaminathan, Michael J. Schulte, Brett Wilkerson, Gabriel H. Loh, Alan Smith, Norman James:
AMD InstinctTM MI250X Accelerator enabled by Elevated Fanout Bridge Advanced Packaging Architecture. VLSI Technology and Circuits 2023: 1-2 - 2021
- [c90]Gabriel H. Loh, Samuel Naffziger, Kevin Lepak:
Understanding Chiplets Today to Anticipate Future Integration Opportunities and Limits. DATE 2021: 142-145 - [c89]Mohamed Assem Ibrahim
Analyzing and Leveraging Decoupled L1 Caches in GPUs. HPCA 2021: 467-478 - [c88]Samuel Naffziger, Noah Beck, Thomas Burd, Kevin Lepak, Gabriel H. Loh, Mahesh Subramony, Sean White:
Pioneering Chiplet Technology and Design for the AMD EPYC™ and Ryzen™ Processor Families : Industrial Product. ISCA 2021: 57-70 - [c87]Jagadish B. Kotra, Michael LeBeane, Mahmut T. Kandemir, Gabriel H. Loh:
Increasing GPU Translation Reach by Leveraging Under-Utilized On-Chip Resources. MICRO 2021: 1169-1181 - [c86]Mark Papermaster, Stephen Kosonocky, Gabriel H. Loh, Samuel Naffziger:
A New Era of Tailored Computing. VLSI Circuits 2021: 1-2 - [i7]Salonik Resch, Anthony Gutierrez, Joon Suk Huh, Srikant Bharadwaj, Yasuko Eckert, Gabriel H. Loh, Mark Oskin, Swamit S. Tannu:
Accelerating Variational Quantum Algorithms Using Circuit Concurrency. CoRR abs/2109.01714 (2021) - 2020
- [c85]Mohamed Assem Ibrahim
Analyzing and Leveraging Shared L1 Caches in GPUs. PACT 2020: 161-173 - [c84]Jieming Yin, Subhash Sethumurugan, Yasuko Eckert, Chintan Patel, Alan Smith, Eric Morton, Mark Oskin, Natalie D. Enright Jerger
Experiences with ML-Driven Design: A NoC Case Study. HPCA 2020: 637-648
2010 – 2019
- 2019
- [c83]Dylan C. Stow, Itir Akgun
Efficient System Architecture in the Era of Monolithic 3D: Dynamic Inter-tier Interconnect and Processing-in-Memory. DAC 2019: 100 - 2018
- [j24]Hyojong Kim, Ramyad Hadidi
CODA: Enabling Co-location of Computation and Data for Multiple GPU Systems. ACM Trans. Archit. Code Optim. 15(3): 32:1-32:23 (2018) - [c82]Joseph L. Greathouse, Gabriel H. Loh:
Machine learning for performance and power modeling of heterogeneous systems. ICCAD 2018: 47 - [c81]Seunghee Shin, Guilherme Cox
Scheduling Page Table Walks for Irregular GPU Applications. ISCA 2018: 180-192 - [c80]Jieming Yin, Zhifeng Lin, Onur Kayiran, Matthew Poremba, Muhammad Shoaib Bin Altaf, Natalie D. Enright Jerger
Modular Routing Design for Chiplet-Based Systems. ISCA 2018: 726-738 - [c79]Ján Veselý, Arkaprava Basu, Abhishek Bhattacharjee
Generic System Calls for GPUs. ISCA 2018: 843-856 - [c78]Amin Farmahini Farahani, Sudhanva Gurumurthi, Gabriel H. Loh, Michael Ignatowski:
Challenges of High-Capacity DRAM Stacks and Potential Directions. MCHPC@SC 2018: 4-13 - [i6]Rachata Ausavarungnirun, Saugata Ghose, Onur Kayiran, Gabriel H. Loh, Chita R. Das, Mahmut T. Kandemir, Onur Mutlu:
Holistic Management of the GPGPU Memory Hierarchy to Manage Warp-level Latency Tolerance. CoRR abs/1804.11038 (2018) - [i5]Rachata Ausavarungnirun, Gabriel H. Loh, Lavanya Subramanian, Kevin K. Chang, Onur Mutlu:
High-Performance and Energy-Effcient Memory Scheduler Design for Heterogeneous Systems. CoRR abs/1804.11043 (2018) - 2017
- [c77]Amro Awad, Arkaprava Basu, Sergey Blagodurov, Yan Solihin, Gabriel H. Loh:
Avoiding TLB Shootdowns Through Self-Invalidating TLB Entries. PACT 2017: 273-287 - [c76]Thiruvengadam Vijayaraghavan, Yasuko Eckert, Gabriel H. Loh, Michael J. Schulte, Mike Ignatowski, Bradford M. Beckmann, William C. Brantley, Joseph L. Greathouse, Wei Huang, Arun Karunanithi, Onur Kayiran, Mitesh R. Meswani, Indrani Paul
Design and Analysis of an APU for Exascale Computing. HPCA 2017: 85-96 - [c75]Andreas Prodromou, Mitesh R. Meswani, Nuwan Jayasena, Gabriel H. Loh, Dean M. Tullsen
MemPod: A Clustered Architecture for Efficient and Scalable Migration in Flat Address Space Multi-level Memories. HPCA 2017: 433-444 - [c74]Dylan C. Stow, Yuan Xie, Taniya Siddiqua, Gabriel H. Loh:
Cost-effective design of scalable high-performance systems using active and passive interposers. ICCAD 2017: 728-735 - [c73]Matthew Poremba, Itir Akgun, Jieming Yin, Onur Kayiran, Yuan Xie, Gabriel H. Loh:
There and Back Again: Optimizing the Interconnect in Networks of Memory Cubes. ISCA 2017: 678-690 - [c72]Abhinav Agrawal, Gabriel H. Loh, James Tuck:
Leveraging near data processing for high-performance checkpoint/restart. SC 2017: 60 - [i4]Ján Veselý, Arkaprava Basu, Abhishek Bhattacharjee, Gabriel H. Loh, Mark Oskin, Steven K. Reinhardt:
GPU System Calls. CoRR abs/1705.06965 (2017) - [i3]Hyojong Kim, Ramyad Hadidi, Lifeng Nai, Hyesoon Kim, Nuwan Jayasena, Yasuko Eckert, Onur Kayiran, Gabriel H. Loh:
CODA: Enabling Co-location of Computation and Data for Near-Data Processing. CoRR abs/1710.09517 (2017) - 2016
- [j23]Ajaykumar Kannan, Natalie D. Enright Jerger
Exploiting Interposer Technologies to Disintegrate and Reintegrate Multicore Processors. IEEE Micro 36(3): 84-93 (2016) - [j22]Rachata Ausavarungnirun, Chris Fallin, Xiangyao Yu, Kevin Kai-Wei Chang, Greg Nazario, Reetuparna Das
A case for hierarchical rings with deflection routing: An energy-efficient on-chip communication substrate. Parallel Comput. 54: 29-45 (2016) - [c71]Onur Kayiran, Adwait Jog, Ashutosh Pattnaik, Rachata Ausavarungnirun, Xulong Tang
μC-States: Fine-grained GPU Datapath Power Management. PACT 2016: 17-30 - [c70]Jieming Yin, Onur Kayiran, Matthew Poremba, Natalie D. Enright Jerger
Efficient synthetic traffic models for large, complex SoCs. HPCA 2016: 297-308 - [c69]Ján Veselý, Arkaprava Basu, Mark Oskin, Gabriel H. Loh, Abhishek Bhattacharjee:
Observations and opportunities in architecting shared virtual memory for heterogeneous systems. ISPASS 2016: 161-171 - [c68]Jia Zhan, Onur Kayiran, Gabriel H. Loh, Chita R. Das, Yuan Xie:
OSCAR: Orchestrating STT-RAM cache traffic for heterogeneous CPU-GPU architectures. MICRO 2016: 28:1-28:13 - [c67]Zhe Wang, Daniel A. Jiménez
Building a Low Latency, Highly Associative DRAM Cache with the Buffered Way Predictor. SBAC-PAD 2016: 109-117 - [i2]Kevin Kai-Wei Chang, Gabriel H. Loh, Mithuna Thottethodi, Yasuko Eckert, Mike O'Connor, Srilatha Manne, Lisa Hsu, Lavanya Subramanian, Onur Mutlu:
Enabling Efficient Dynamic Resizing of Large DRAM Caches via A Hardware Consistent Hashing Mechanism. CoRR abs/1602.00722 (2016) - [i1]Rachata Ausavarungnirun, Chris Fallin, Xiangyao Yu, Kevin Kai-Wei Chang, Greg Nazario, Reetuparna Das, Gabriel H. Loh, Onur Mutlu:
Achieving both High Energy Efficiency and High Performance in On-Chip Communication using Hierarchical Rings with Deflection Routing. CoRR abs/1602.06005 (2016) - 2015
- [j21]Michael J. Schulte, Mike Ignatowski, Gabriel H. Loh, Bradford M. Beckmann, William C. Brantley, Sudhanva Gurumurthi, Nuwan Jayasena, Indrani Paul
Achieving Exascale Capabilities through Heterogeneous Computing. IEEE Micro 35(4): 26-36 (2015) - [j20]Daehyun Kim, Krit Athikulwongse, Michael B. Healy, Mohammad M. Hossain, Moongon Jung, Ilya Khorosh, Gokul Kumar, Young-Joon Lee, Dean L. Lewis, Tzu-Wei Lin, Chang Liu, Shreepad Panth, Mohit Pathak, Minzhen Ren, Guanhao Shen, Taigon Song, Dong Hyuk Woo, Xin Zhao, Joungho Kim, Ho Choi, Gabriel H. Loh, Hsien-Hsin S. Lee, Sung Kyu Lim
Design and Analysis of 3D-MAPS (3D Massively Parallel Processor with Stacked Memory). IEEE Trans. Computers 64(1): 112-125 (2015) - [c66]Rachata Ausavarungnirun, Saugata Ghose, Onur Kayiran, Gabriel H. Loh, Chita R. Das, Mahmut T. Kandemir, Onur Mutlu:
Exploiting Inter-Warp Heterogeneity to Improve GPGPU Performance. PACT 2015: 25-38 - [c65]Mark Oskin, Gabriel H. Loh:
A Software-Managed Approach to Die-Stacked DRAM. PACT 2015: 188-200 - [c64]Mitesh R. Meswani, Sergey Blagodurov, David Roberts, John Slice, Mike Ignatowski, Gabriel H. Loh:
Heterogeneous memory architectures: A HW/SW approach for mixing die-stacked and off-package memories. HPCA 2015: 126-136 - [c63]Gabriel H. Loh, Natalie D. Enright Jerger
Interconnect-Memory Challenges for Multi-chip, Silicon Interposer Systems. MEMSYS 2015: 3-10 - [c62]Chun-Yi Su, David Roberts, Edgar A. León
HpMC: An Energy-aware Management System of Multi-level Memory Architectures. MEMSYS 2015: 167-178 - [c61]Binh Pham, Ján Veselý, Gabriel H. Loh, Abhishek Bhattacharjee:
Large pages and lightweight memory management in virtualized environments: can you have it both ways? MICRO 2015: 1-12 - [c60]Ajaykumar Kannan, Natalie D. Enright Jerger
Enabling interposer-based disintegration of multi-core processors. MICRO 2015: 546-558 - 2014
- [j19]Jaewoong Sim, Gabriel H. Loh, Vilas Sridharan, Mike O'Connor
A Configurable and Strong RAS Solution for Die-Stacked DRAM Caches. IEEE Micro 34(3): 80-90 (2014) - [c59]Binh Pham, Abhishek Bhattacharjee, Yasuko Eckert, Gabriel H. Loh:
Increasing TLB reach by exploiting clustering in page translations. HPCA 2014: 558-567 - [c58]Yingying Tian, Samira Manabi Khan, Daniel A. Jiménez
Last-level cache deduplication. ICS 2014: 53-62 - [c57]Hyeran Jeon, Gabriel H. Loh, Murali Annavaram
Efficient RAS support for die-stacked DRAM. ITC 2014: 1-10 - [c56]Djordje Jevdjic, Gabriel H. Loh, Cansu Kaynak, Babak Falsafi:
Unison Cache: A Scalable and Effective Die-Stacked DRAM Cache. MICRO 2014: 25-37 - [c55]Onur Kayiran, Nachiappan Chidambaram Nachiappan
Managing GPU Concurrency in Heterogeneous Architectures. MICRO 2014: 114-126 - [c54]Natalie D. Enright Jerger
NoC Architectures for Silicon Interposer Systems: Why Pay for more Wires when you Can Get them (from your interposer) for Free? MICRO 2014: 458-470 - [c53]Rachata Ausavarungnirun, Chris Fallin, Xiangyao Yu, Kevin Kai-Wei Chang, Greg Nazario, Reetuparna Das
Design and Evaluation of Hierarchical Rings with Deflection Routing. SBAC-PAD 2014: 230-237 - [c52]Mitesh R. Meswani, Gabriel H. Loh, Sergey Blagodurov, David Roberts, John Slice, Mike Ignatowski:
Toward efficient programmer-managed two-level memory hierarchies in exascale computers. Co-HPC@SC 2014: 9-16 - [c51]Niladrish Chatterjee, Mike O'Connor
Managing DRAM Latency Divergence in Irregular GPGPU Applications. SC 2014: 128-139 - 2013
- [j18]Babak Falsafi, Gabriel H. Loh:
Top Picks from the 2012 Computer Architecture Conferences. IEEE Micro 33(3): 4-7 (2013) - [j17]Jishen Zhao, Guangyu Sun, Gabriel H. Loh, Yuan Xie:
Optimizing GPU energy efficiency with 3D die-stacking graphics memory and reconfigurable memory interface. ACM Trans. Archit. Code Optim. 10(4): 24:1-24:25 (2013) - [j16]Yuan Xie, Gabriel H. Loh:
Guest Editorial. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 32(4): 485-486 (2013) - [c50]Jaewoong Sim, Gabriel H. Loh, Vilas Sridharan, Mike O'Connor
Resilient die-stacked DRAM caches. ISCA 2013: 416-427 - 2012
- [j15]Kiyoung Choi, John Kim
Guest Editorial New Interconnect Technologies in On-Chip Communication. IEEE J. Emerg. Sel. Topics Circuits Syst. 2(2): 121-123 (2012) - [j14]John Kim
Exploiting New Interconnect Technologies in On-Chip Communication. IEEE J. Emerg. Sel. Topics Circuits Syst. 2(2): 124-136 (2012) - [j13]Gabriel H. Loh, Mark D. Hill:
Supporting Very Large DRAM Caches with Compound-Access Scheduling and MissMap. IEEE Micro 32(3): 70-78 (2012) - [c49]Rachata Ausavarungnirun, Kevin Kai-Wei Chang, Lavanya Subramanian, Gabriel H. Loh, Onur Mutlu:
Staged memory scheduling: Achieving high performance and scalability in heterogeneous systems. ISCA 2012: 416-427 - [c48]Jishen Zhao, Guangyu Sun, Gabriel H. Loh, Yuan Xie:
Energy-efficient GPU design with reconfigurable in-package graphics memory. ISLPED 2012: 403-408 - [c47]Dae Hyun Kim, Krit Athikulwongse, Michael B. Healy, Mohammad M. Hossain, Moongon Jung, Ilya Khorosh, Gokul Kumar, Young-Joon Lee, Dean L. Lewis, Tzu-Wei Lin, Chang Liu, Shreepad Panth, Mohit Pathak, Minzhen Ren, Guanhao Shen, Taigon Song, Dong Hyuk Woo, Xin Zhao, Joungho Kim, Ho Choi, Gabriel H. Loh, Hsien-Hsin S. Lee, Sung Kyu Lim
3D-MAPS: 3D Massively parallel processor with stacked memory. ISSCC 2012: 188-190 - [c46]Moinuddin K. Qureshi, Gabriel H. Loh:
Fundamental Latency Trade-off in Architecting DRAM Caches: Outperforming Impractical SRAM-Tags with a Simple and Practical Design. MICRO 2012: 235-246 - [c45]Jaewoong Sim, Gabriel H. Loh, Hyesoon Kim, Mike O'Connor
A Mostly-Clean DRAM Cache for Effective Hit Speculation and Self-Balancing Dispatch. MICRO 2012: 247-257 - [c44]Gabriel H. Loh:
Computer architecture for die stacking. VLSI-DAT 2012: 1-2 - 2011
- [c43]Yuejian Xie, Gabriel H. Loh:
Thread-aware dynamic shared cache compression in multi-core processors. ICCD 2011: 135-141 - [c42]Andrew W. Hay, Karin Strauss, Timothy Sherwood
Preventing PCM banks from seizing too much power. MICRO 2011: 186-195 - [c41]Gabriel H. Loh:
A register-file approach for row buffer caches in die-stacked DRAMs. MICRO 2011: 351-361 - [c40]Gabriel H. Loh, Mark D. Hill:
Efficiently enabling conventional block sizes for very large die-stacked DRAM caches. MICRO 2011: 454-464 - 2010
- [j12]Gabriel H. Loh, Yuan Xie:
3D Stacked Microprocessor: Are We There Yet? IEEE Micro 30(3): 60-64 (2010) - [c39]Michael B. Healy, Krit Athikulwongse, Rohan Goel, Mohammad M. Hossain, Dae Hyun Kim, Young-Joon Lee, Dean L. Lewis, Tzu-Wei Lin, Chang Liu, Moongon Jung, Brian Ouellette, Mohit Pathak, Hemant Sane, Guanhao Shen, Dong Hyuk Woo, Xin Zhao, Gabriel H. Loh, Hsien-Hsin S. Lee
Design and analysis of 3D-MAPS: A many-core 3D processor with stacked memory. CICC 2010: 1-4 - [c38]Serkan Ozdemir, Yan Pan, Abhishek Das, Gokhan Memik, Gabriel H. Loh, Alok N. Choudhary:
Quantifying and coping with parametric variations in 3D-stacked microarchitectures. DAC 2010: 144-149 - [c37]Yuejian Xie, Gabriel H. Loh:
Scalable Shared-Cache Management by Containing Thrashing Workloads. HiPEAC 2010: 262-276 - [c36]Stuart E. Schechter, Gabriel H. Loh, Karin Strauss, Doug Burger:
Use ECP, not ECC, for hard failures in resistive memories. ISCA 2010: 141-152
2000 – 2009
- 2009
- [j11]Samantika Subramaniam, Gabriel H. Loh:
Design and optimization of the store vectors memory dependence predictor. ACM Trans. Archit. Code Optim. 6(4): 16:1-16:33 (2009) - [j10]Kiran Puttaswamy, Gabriel H. Loh:
3D-Integrated SRAM Components for High-Performance Microprocessors. IEEE Trans. Computers 58(10): 1369-1381 (2009) - [c35]Michael B. Healy, Hsien-Hsin S. Lee, Gabriel H. Loh, Sung Kyu Lim
Thermal optimization in multi-granularity multi-core floorplanning. ASP-DAC 2009: 43-48 - [c34]Samantika Subramaniam, Anne Bracy, Hong Wang, Gabriel H. Loh:
Criticality-based optimizations for efficient load processing. HPCA 2009: 419-430 - [c33]Yuejian Xie, Gabriel H. Loh:
PIPP: promotion/insertion pseudo-partitioning of multi-core shared caches. ISCA 2009: 174-183 - [c32]Gabriel H. Loh, Samantika Subramaniam, Yuejian Xie:
Zesto: A cycle-level simulator for highly detailed microarchitecture exploration. ISPASS 2009: 53-64 - [c31]Gabriel H. Loh:
Extending the effectiveness of 3D-stacked DRAM caches with an adaptive multi-queue policy. MICRO 2009: 201-212 - 2008
- [j9]Gabriel H. Loh, Daniel A. Jiménez:
Modulo Path History for the Reduction of Pipeline Overheads in Path-based Neural Branch Predictors. Int. J. Parallel Program. 36(2): 267-286 (2008) - [c30]Gabriel H. Loh:
A modular 3d processor for flexible product design and technology migration. Conf. Computing Frontiers 2008: 159-170 - [c29]Samantika Subramaniam, Milos Prvulovic, Gabriel H. Loh:
PEEP: Exploiting predictability of memory dependences in SMT processors. HPCA 2008: 137-148 - [c28]Gabriel H. Loh:
3D-Stacked Memory Architectures for Multi-core Processors. ISCA 2008: 453-464 - [c27]Maurício Breternitz Jr.
A Segmented Bloom Filter Algorithm for Efficient Predictors. SBAC-PAD 2008: 123-130 - 2007
- [j8]Gabriel H. Loh, Yuan Xie, Bryan Black:
Processor Design in 3D Die-Stacking Technologies. IEEE Micro 27(3): 31-48 (2007) - [j7]Michael B. Healy, Mario Vittes, Mongkol Ekpanyapong, Chinnakrishnan S. Ballapuram, Sung Kyu Lim
Multiobjective Microarchitectural Floorplanning for 2-D and 3-D ICs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(1): 38-52 (2007) - [j6]Peter G. Sassone, D. Scott Wills, Gabriel H. Loh:
Static strands: Safely exposing dependence chains for increasing embedded power efficiency. ACM Trans. Embed. Comput. Syst. 6(4): 24 (2007) - [c26]Kiran Puttaswamy, Gabriel H. Loh:
Scalability of 3D-Integrated Arithmetic Units in High-Performance Microprocessors. DAC 2007: 622-625 - [c25]Kiran Puttaswamy, Gabriel H. Loh:
Thermal Herding: Microarchitecture Techniques for Controlling Hotspots in High-Performance 3D-Integrated Processors. HPCA 2007: 193-204 - [c24]Peter G. Sassone, Jeff Rupley, Edward Brekelbaum, Gabriel H. Loh, Bryan Black:
Matrix scheduler reloaded. ISCA 2007: 335-346 - 2006
- [j5]Yuan Xie, Gabriel H. Loh, Bryan Black, Kerry Bernstein:
Design space exploration for 3D architectures. ACM J. Emerg. Technol. Comput. Syst. 2(2): 65-103 (2006) - [c23]Chinnakrishnan S. Ballapuram, Kiran Puttaswamy, Gabriel H. Loh, Hsien-Hsin S. Lee:
Entropy-based low power data TLB design. CASES 2006: 304-311 - [c22]Michael B. Healy, Mario Vittes, Mongkol Ekpanyapong, Chinnakrishnan S. Ballapuram, Sung Kyu Lim, Hsien-Hsin S. Lee, Gabriel H. Loh:
Microarchitectural floorplanning under performance and thermal tradeoff. DATE 2006: 1288-1293 - [c21]Kiran Puttaswamy, Gabriel H. Loh:
Thermal analysis of a 3D die-stacked high-performance microprocessor. ACM Great Lakes Symposium on VLSI 2006: 19-24 - [c20]Kiran Puttaswamy, Gabriel H. Loh:
Dynamic instruction schedulers in a 3-dimensional integration technology. ACM Great Lakes Symposium on VLSI 2006: 153-158 - [c19]Samantika Subramaniam, Gabriel H. Loh:
Store vectors for scalable memory dependence prediction and scheduling. HPCA 2006: 65-76 - [c18]Kiran Puttaswamy, Gabriel H. Loh:
The impact of 3-dimensional integration on the design of arithmetic units. ISCAS 2006 - [c17]Gabriel H. Loh:
Revisiting the performance impact of branch predictor latencies. ISPASS 2006: 59-69 - [c16]Kiran Puttaswamy, Gabriel H. Loh:
Implementing Register Files for High-Performance Microprocessors in a Die-Stacked (3D) Technology. ISVLSI 2006: 384-392 - [c15]Samantika Subramaniam, Gabriel H. Loh:
Fire-and-Forget: Load/Store Scheduling with No Store Queue at All. MICRO 2006: 273-284 - [c14]Ranjith Subramanian, Yannis Smaragdakis, Gabriel H. Loh:
Adaptive Caches: Effective Shaping of Cache Behavior to Workloads. MICRO 2006: 385-396 - [c13]Bryan Black, Murali Annavaram
Die Stacking (3D) Microarchitecture. MICRO 2006: 469-479 - [c12]Daniel A. Jiménez, Gabriel H. Loh:
Controlling the Power and Area of Neural Branch Predictors for Practical Implementation in High-Performance Processors. SBAC-PAD 2006: 55-62 - 2005
- [j4]Gabriel H. Loh:
Deconstructing the Frankenpredictor for Implementable Branch Predictors. J. Instr. Level Parallelism 7 (2005) - [c11]Gabriel H. Loh:
A Simple Divide-and-Conquer Approach for Neural-Class Branch Prediction. IEEE PACT 2005: 243-254 - [c10]Kiran Puttaswamy, Gabriel H. Loh:
Implementing Caches in a 3D Technology for High Performance Processors. ICCD 2005: 525-532 - [c9]Gabriel H. Loh:
Simulation Differences Between Academia and Industry: A Branch Prediction Case Study. ISPASS 2005: 21-31 - [c8]Peter G. Sassone, D. Scott Wills, Gabriel H. Loh:
Static strands: safely collapsing dependence chains for increasing embedded power efficiency. LCTES 2005: 127-136 - 2003
- [j3]Gabriel H. Loh:
Width-Partitioned Load Value Predictors. J. Instr. Level Parallelism 5 (2003) - [j2]Gabriel H. Loh, Dana S. Henry, Arvind Krishnamurthy:
Exploiting Bias in the Hysteresis Bit of 2-bit Saturating Counters in Branch Predictors. J. Instr. Level Parallelism 5 (2003) - 2002
- [j1]Bradley C. Kuszmaul, Dana S. Henry, Gabriel H. Loh:
A Comparison of Asymptotically Scalable Superscalar Processors. Theory Comput. Syst. 35(2): 129-150 (2002) - [c7]Gabriel H. Loh, Dana S. Henry:
Predicting Conditional Branches With Fusion-Based Hybrid Predictors. IEEE PACT 2002: 165-176 - [c6]Gabriel H. Loh, Dana S. Henry:
Applying Machine Learning for Ensemble Branch Predictors. IEA/AIE 2002: 264-274 - [c5]Dana S. Henry, Gabriel H. Loh, Rahul Sami:
Speculative Clustered Caches for Clustered Processors. ISHPC 2002: 281-290 - [c4]Gabriel H. Loh:
Exploiting data-width locality to increase superscalar execution bandwidth. MICRO 2002: 395-405 - 2001
- [c3]Gabriel H. Loh:
A time-stamping algorithm for efficient performance estimation of superscalar processors. SIGMETRICS/Performance 2001: 72-81 - 2000
- [c2]Dana S. Henry, Bradley C. Kuszmaul, Gabriel H. Loh, Rahul Sami:
Circuits for wide-window superscalar processors. ISCA 2000: 236-247
1990 – 1999
- 1999
- [c1]Bradley C. Kuszmaul, Dana S. Henry, Gabriel H. Loh:
A Comparison of Scalable Superscalar Processors. SPAA 1999: 126-137
Coauthor Index
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