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Michael B. Healy

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2020 – today

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2024
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  - journals/corr/abs-2408-06469
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Michael B. Healy, Reza Jokar, Soolu Thomas, Vincent R. Pascuzzi, Kit Barton, Thomas A. Alexander, Roy Elkabetz, Brian C. Donovan, Hiroshi Horii, Marius Hillenbrand:
Design and architecture of the IBM Quantum Engine Compiler. CoRR abs/2408.06469 (2024)

2010 – 2019

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2019
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Seokin Hong, Bülent Abali, Alper Buyuktosunoglu, Michael B. Healy, Prashant J. Nair:
Touché: Towards Ideal and Efficient Cache Compression By Mitigating Tag Area Overheads. MICRO 2019: 453-465
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  - journals/corr/abs-1909-00553
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Seokin Hong, Bülent Abali, Alper Buyuktosunoglu, Michael B. Healy, Prashant J. Nair:
Touché: Towards Ideal and Efficient Cache Compression By Mitigating Tag Area Overheads. CoRR abs/1909.00553 (2019)
2018
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Ben Lin, Michael B. Healy, Rustam Miftakhutdinov, Philip G. Emma, Yale N. Patt:
Duplicon Cache: Mitigating Off-Chip Memory Bank and Bank Group Conflicts Via Data Duplication. MICRO 2018: 285-297
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Seokin Hong, Prashant Jayaprakash Nair, Bülent Abali, Alper Buyuktosunoglu, Kyu-Hyoun Kim, Michael B. Healy:
Attaché: Towards Ideal Memory Compression by Mitigating Metadata Bandwidth Overheads. MICRO 2018: 326-338
2017
[c15]
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Michael B. Healy, Seokin Hong:
CramSim: controller and memory simulator. MEMSYS 2017: 83-85
2015
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Daehyun Kim, Krit Athikulwongse, Michael B. Healy, Mohammad M. Hossain, Moongon Jung, Ilya Khorosh, Gokul Kumar, Young-Joon Lee, Dean L. Lewis, Tzu-Wei Lin, Chang Liu, Shreepad Panth, Mohit Pathak, Minzhen Ren, Guanhao Shen, Taigon Song, Dong Hyuk Woo, Xin Zhao, Joungho Kim, Ho Choi, Gabriel H. Loh, Hsien-Hsin S. Lee, Sung Kyu Lim:
Design and Analysis of 3D-MAPS (3D Massively Parallel Processor with Stacked Memory). IEEE Trans. Computers 64(1): 112-125 (2015)
2014
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Philip G. Emma, Alper Buyuktosunoglu, Michael B. Healy, Krishnan Kailas, Valentin Puente, Roy Yu, Allan Hartstein, Pradip Bose, Jaime H. Moreno, Eren Kursun:
3D stacking of high-performance processors. HPCA 2014: 500-511
2012
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  - journals/tvlsi/HealyL12
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Michael B. Healy, Sung Kyu Lim:
Distributed TSV Topology for 3-D Power-Supply Networks. IEEE Trans. Very Large Scale Integr. Syst. 20(11): 2066-2079 (2012)
[c13]
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Pradip Bose, Alper Buyuktosunoglu, John A. Darringer, Meeta Sharma Gupta, Michael B. Healy, Hans M. Jacobson, Indira Nair, Jude A. Rivers, Jeonghee Shin, Augusto Vega, Alan J. Weger:
Power management of multi-core chips: Challenges and pitfalls. DATE 2012: 977-982
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Dae Hyun Kim, Krit Athikulwongse, Michael B. Healy, Mohammad M. Hossain, Moongon Jung, Ilya Khorosh, Gokul Kumar, Young-Joon Lee, Dean L. Lewis, Tzu-Wei Lin, Chang Liu, Shreepad Panth, Mohit Pathak, Minzhen Ren, Guanhao Shen, Taigon Song, Dong Hyuk Woo, Xin Zhao, Joungho Kim, Ho Choi, Gabriel H. Loh, Hsien-Hsin S. Lee, Sung Kyu Lim:
3D-MAPS: 3D Massively parallel processor with stacked memory. ISSCC 2012: 188-190
2011
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Michael B. Healy, Fayez Mohamood, Hsien-Hsin S. Lee, Sung Kyu Lim:
Integrated microarchitectural floorplanning and run-time controller for inductive noise mitigation. ACM Trans. Design Autom. Electr. Syst. 16(4): 46:1-46:25 (2011)
[c11]
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Michael B. Healy, Sung Kyu Lim:
A novel TSV topology for many-tier 3D power-delivery networks. DATE 2011: 261-264
[c10]
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Michael B. Healy, Sung Kyu Lim:
Power-supply-network design in 3D integrated systems. ISQED 2011: 223-228
[c9]
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  - conf/socc/ShinDLALNH11
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Jeonghee Shin, John A. Darringer, Guojie Luo, Merav Aharoni, Alexey Lvov, Gi-Joon Nam, Michael B. Healy:
Floorplanning challenges in early chip planning. SoCC 2011: 388-393
2010
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  - conf/cicc/HealyAGHKLLLLJOPSSWZLLL10
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Michael B. Healy, Krit Athikulwongse, Rohan Goel, Mohammad M. Hossain, Dae Hyun Kim, Young-Joon Lee, Dean L. Lewis, Tzu-Wei Lin, Chang Liu, Moongon Jung, Brian Ouellette, Mohit Pathak, Hemant Sane, Guanhao Shen, Dong Hyuk Woo, Xin Zhao, Gabriel H. Loh, Hsien-Hsin S. Lee, Sung Kyu Lim:
Design and analysis of 3D-MAPS: A many-core 3D processor with stacked memory. CICC 2010: 1-4

2000 – 2009

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2009
[c7]
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Michael B. Healy, Hsien-Hsin S. Lee, Gabriel H. Loh, Sung Kyu Lim:
Thermal optimization in multi-granularity multi-core floorplanning. ASP-DAC 2009: 43-48
2008
[c6]
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Michael B. Healy, Fayez Mohamood, Hsien-Hsin S. Lee, Sung Kyu Lim:
A unified methodology for power supply noise reduction in modern microarchitecture design. ASP-DAC 2008: 611-616
2007
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  - journals/tcad/HealyVEBLLL07
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Michael B. Healy, Mario Vittes, Mongkol Ekpanyapong, Chinnakrishnan S. Ballapuram, Sung Kyu Lim, Hsien-Hsin S. Lee, Gabriel H. Loh:
Multiobjective Microarchitectural Floorplanning for 2-D and 3-D ICs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(1): 38-52 (2007)
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Fayez Mohamood, Michael B. Healy, Sung Kyu Lim, Hsien-Hsin S. Lee:
Noise-Direct: A Technique for Power Supply Noise Aware Floorplanning Using Microarchitecture Profiling. ASP-DAC 2007: 786-791
2006
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Mongkol Ekpanyapong, Michael B. Healy, Sung Kyu Lim:
Profile-Driven Instruction Mapping for Dataflow Architectures. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(12): 3017-3025 (2006)
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Michael B. Healy, Mario Vittes, Mongkol Ekpanyapong, Chinnakrishnan S. Ballapuram, Sung Kyu Lim, Hsien-Hsin S. Lee, Gabriel H. Loh:
Microarchitectural floorplanning under performance and thermal tradeoff. DATE 2006: 1288-1293
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Fayez Mohamood, Michael B. Healy, Sung Kyu Lim, Hsien-Hsin S. Lee:
A Floorplan-Aware Dynamic Inductive Noise Controller for Reliable Processor Design. MICRO 2006: 3-14
2005
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Mongkol Ekpanyapong, Michael B. Healy, Sung Kyu Lim:
Placement for configurable dataflow architecture. ASP-DAC 2005: 1127-1130
[c1]
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Michael B. Healy, Mongkol Ekpanyapong, Sung Kyu Lim:
MILP-based Placement and Routing for Dataflow Architecture. FPL 2005: 71-76

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