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Design space exploration for 3D architectures

Authors:

Gabriel H. Loh,

Kerry BernsteinAuthors Info & Claims

ACM Journal on Emerging Technologies in Computing Systems (JETC), Volume 2, Issue 2

Pages 65 - 103

https://doi.org/10.1145/1148015.1148016

Published: 01 April 2006 Publication History

Abstract

As technology scales, interconnects have become a major performance bottleneck and a major source of power consumption for microprocessors. Increasing interconnect costs make it necessary to consider alternate ways of building modern microprocessors. One promising option is 3D architectures where a stack of multiple device layers with direct vertical tunneling through them are put together on the same chip. As fabrication of 3D integrated circuits has become viable, developing CAD tools and architectural techniques is imperative to explore the design space to 3D microarchitectures. In this article, we give a brief introduction to 3D integration technology, discuss the EDA design tools that can enable the adoption of 3D ICs, and present the implementation of various microprocessor components using 3D technology. An industrial case study is presented as an initial attempt to design 3D microarchitectures.

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Index Terms

Design space exploration for 3D architectures
1. Computer systems organization
  1. Architectures
2. Hardware
  1. Integrated circuits

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Published In

cover image ACM Journal on Emerging Technologies in Computing Systems

ACM Journal on Emerging Technologies in Computing Systems Volume 2, Issue 2

April 2006

90 pages

ISSN:1550-4832

EISSN:1550-4840

DOI:10.1145/1148015

Issue’s Table of Contents

Copyright © 2006 ACM.

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Association for Computing Machinery

New York, NY, United States

Journal Family

ACM Journals for the Design of Smart and Connected Systems

Publication History

Published: 01 April 2006

Published in JETC Volume 2, Issue 2

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Cited By

Najibi HLevisse AAnsaloni GZapater MVasic MAtienza D(2023)Thermal and Voltage-Aware Performance Management of 3-D MPSoCs With Flow Cell Arrays and Integrated SC ConvertersIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2022.316825742:1(2-15)Online publication date: Jan-2023
https://doi.org/10.1109/TCAD.2022.3168257
Sargentis GFrangedaki EChiotinis MKoutsoyiannis DCamarinopoulos SCamarinopoulos ALagaros N(2022)3D Scanning/Printing: A Technological Stride in SculptureTechnologies10.3390/technologies1001000910:1(9)Online publication date: 14-Jan-2022
https://doi.org/10.3390/technologies10010009
Ali MRahman MIbrahim AAl-Naeem MHossain E(2022)A High Static Performance Hierarchical Three-Dimensional Shifted Completely Connected NetworkIEEE Access10.1109/ACCESS.2022.316872810(43812-43836)Online publication date: 2022
https://doi.org/10.1109/ACCESS.2022.3168728
Xiao YNazarian SBogdan P(2021)Plasticity-on-Chip Design: Exploiting Self-Similarity for Data CommunicationsIEEE Transactions on Computers10.1109/TC.2021.307150770:6(950-962)Online publication date: 1-Jun-2021
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Artho CPhan QAldous PAlmaawi ABang LBerglund LBultan TChen ZConverse HDong WEiers WGligoric MGoldsmith SGrunske LHooker JKadron IKehrer TKhurshid SLe XLo DMercer EMisailovic SNamakonov ELam Nguyen HNoller YOgles BPadhye RParizek PPăsăreanu CPowell SSaha SSen KSherman EStorey KTang MVisser WWang JYu H(2020)The Java Pathfinder Workshop 2019ACM SIGSOFT Software Engineering Notes10.1145/3385678.338568545:2(20-22)Online publication date: 3-May-2020
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Shin HChung E(2019)In-DRAM Cache Management for Low Latency and Low Power 3D-Stacked DRAMsMicromachines10.3390/mi1002012410:2(124)Online publication date: 14-Feb-2019
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Asad AFazeli MJahed-Motlagh MFathy MMohammadi F(2019)An Energy-efficient Reliable Heterogeneous Uncore Architecture for Future 3D Chip-multiprocessorsJournal of Circuits, Systems and Computers10.1142/S0218126619502244Online publication date: 8-Feb-2019
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