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SIGARCH Computer Architecture News 15(5), SIGOPS Operating System Review 21(4), SIGPLAN Notices 22(10)

• 
  Niklaus Wirth:
  Hardware Architectures for Programming Languages and Programming Languages for Hardware Architectures. 2-8

• 
  Bob Beck, Bob Kasten, Shreekant S. Thakkar:
  VLSI Assist For a Multiprocessor. 10-20
• 
  Roberto Bisiani, Alessandro Forin:
  Architectural Support for Multilanguage Parallel Programming on Heterogeneous Systems. 21-30
• 
  Richard F. Rashid, Avadis Tevanian, Michael Young, David B. Golub, Robert V. Baron, David L. Black, William J. Bolosky, Jonathan Chew:
  Machine-Independent Virtual Memory Management for Paged Uniprocessor and Multiprocessor Architectures. 31-39

• 
  John R. Hayes, Martin E. Fraeman, Robert L. Williams, Thomas Zaremba:
  An Architecture for the Direct Execution of the Forth Programming Language. 42-49
• 
  Peter Steenkiste, John L. Hennessy:
  Tags and Type Checking in Lisp: Hardware and Software Approaches. 50-59
• 
  Jack W. Davidson, Richard A. Vaughan:
  The Effect of Instruction Set Complexity on Program Size and Memory Performance. 60-64
• 
  Russell R. Atkinson, Edward M. McCreight:
  The Dragon Processor. 65-69

• 
  James R. Goodman:
  Coherency for Multiprocessor Virtual Address Caches. 72-81
• 
  Thomas A. Cargill, Bart N. Locanthi:
  Cheap Hardware Support for Software Debugging and Profiling. 82-83
• 
  Christos J. Georgiou, S. L. Palmer, Philip L. Rosenfeld:
  An Experimental Coprocessor for Implementing Persistant Objects on an IBM 4381. 84-87

• 
  Daniel J. Magenheimer, Liz Peters, Karl Pettis, Dan Zuras:
  Integer Multiplication and Division on the HP Precision Architecture. 90-99
• 
  David W. Wall, Michael L. Powell:
  The Mahler Experience: Using and Intermediate Language as the Machine Description. 100-104
• 
  Shlomo Weiss, James E. Smith:
  A Study of Scalar Compilation Techniques for Pipelined Supercomputers. 105-109

• 
  William R. Bush, A. Dain Samples, David M. Ungar, Paul N. Hilfinger:
  Compiling Smalltalk-80 to a RISC. 112-116
• 
  Fred C. Chow, Steven Correll, Mark I. Himelstein, Earl Killian, Larry Weber:
  How Many Addressing Modes are Enough? 117-121
• 
  Henry Massalin:
  Superoptimizer - A Look at the Smallest Program. 122-126

• 
  Kazuo Taki, Katsuto Nakajima, Hiroshi Nakashima, Morihiro Ikeda:
  Performance and Architectural Evaluation of the PSI Machine. 128-135
• 
  Gaetano Borriello, Andrew R. Cherenson, Peter B. Danzig, Michael N. Nelson:
  RISCs versus CISCs for Prolog: A Case Study. 136-145
• 
  Richard B. Kieburtz:
  A RISC Architecture for Symbolic Computation. 146-155

• 
  David R. Ditzel, Hubert R. McLellan:
  Design Tradeoffs to Support the C Programming Language in the CRISP Microprocessor. 158-163
• 
  Charles P. Thacker, Lawrence C. Stewart:
  Firefly: A Multiprocessor Workstation. 164-172
• 
  Douglas W. Clark:
  Pipelining and Performance in the VAX 8800 Processor. 173-177

• 
  Robert P. Colwell, Robert P. Nix, John J. O'Donnell, David B. Papworth, Paul K. Rodman:
  A VLIW Architecture for a Trace Scheduling Compiler. 180-192
• 
  Adam Levinthal, Pat Hanrahan, Mike Paquette, Jim Lawson:
  Parallel Computers for Graphics Applications. 193-198
• 
  James E. Smith, Gregory E. Dermer, B. D. Vanderwarn, S. D. Klinger, C. M. Rozewski, D. L. Fowler, K. R. Scidmore, James Laudon:
  The ZS-1 Central Processor. 199-204

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last updated on 2025-01-10 18:40 CET by the dblp team

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