More Web Proxy on the site http://driver.im/

article

Free access

A VLIW architecture for a trace scheduling compiler

Authors:

Robert P. Colwell,

John J. O'Donnell,

David B. Papworth,

Paul K. RodmanAuthors Info & Claims

ACM SIGARCH Computer Architecture News, Volume 15, Issue 5

Pages 180 - 192

https://doi.org/10.1145/36177.36201

Published: 01 October 1987 Publication History

Abstract

Very Long Instruction Word (VLIW) architectures were promised to deliver far more than the factor of two or three that current architectures achieve from overlapped execution. Using a new type of compiler which compacts ordinary sequential code into long instruction words, a VLIW machine was expected to provide from ten to thirty times the performance of a more conventional machine built of the same implementation technology.Multiflow Computer, Inc., has now built a VLIW called the TRACE^TM along with its companion Trace Scheduling^TM compacting compiler. This new machine has fulfilled the performance promises that were made. Using many fast functional units in parallel, this machine extends some of the basic Reduced-Instruction-Set precepts: the architecture is load/store, the microarchitecture is exposed to the compiler, there is no microcode, and there is almost no hardware devoted to synchronization, arbitration, or interlocking of any kind (the compiler has sole responsibility for runtime resource usage).This paper discusses the design of this machine and presents some initial performance results.

References

[1]

Kate85. Manolis Katevenis, Reduced Instruction Set Computer Architectures for VLSI, MIT Press, Cambridge, Mass., 1985.

Digital Library

[2]

Tjad70. G. S. Tjaden and M. J. Flynn, "Detection and parallel execution of independent instructions," Transactions on Computers, vol. C-19, no. 10, pp. 889--895, IEEE, October 1970.

[3]

Fost72. C. C. Foster and E. M. Riseman, "Percolation of code to enhance parallel dispatching and execution," Transactions on Computers, vol. C-21, no. 12, pp. 1411--1415, IEEE, December 1972.

[4]

Fish83. Joseph A. Fisher, "Very Long Instruction Word Architectures and the ELI-512," Proceedings of the 10th Symposium on Computer Architectures, pp. 140--150, IEEE, June, 1983.

Digital Library

[5]

Elli86.John R. Ellis, Bulldog: A Compiler for VLIW Architectures, MIT Press, Cambridge, Mass., 1986.

Digital Library

[6]

Fish79. Joseph A. Fisher, "The Optimization of Horizontal Microcode Within and Beyond Basic Blocks: An Application of Processor Scheduling with Resources," Technical Report COO-3077--161, Courant Mathematics and Computing Laboratory, New York University, October 1979.

[7]

Henn81. John L. Hennessy, N. Jouppi, F. Baskett, and J. Gill, "MIPS: A VLSI processor architecture," Proceedings of the CMU Conference on VLSI Systems and Computations, pp. 337--346, Computer Science Press, October 1981.

[8]

Radi82. George Radin, "The 801 Minicomputer," Proceedings SIGARCH/SIGPLAN Symposium on Architectural Support for Programming Languages and Operating Systems, pp. 39--47, ACM, March 1982.

Digital Library

[9]

Toma82. Robert M. Tomasulo, "An Efficient Algorithm for Exploiting Multiple Arithmetic Units," Computer Structures: Principles and Examples, pp. 293--305, McGraw-Hill, 1982.

Digital Library

[10]

Thor70. James E. Thornton, Design of a Computer: The Control Data 6600, Scott, Foresman &amp; Company, Glenview, Illinois, 1970.

Digital Library

[11]

Acos86. R. D. Acosta, J. Kjelstrup, and H. C. Torng, "An Instruction Issuing Approach to Enhancing Performance in Multiple Functional Unit Processors," IEEE Transactions on Computers, vol. C-35, no. 9, pp. 815--828, September, 1986.

Digital Library

[12]

Seit85. Charles Seitz, "The cosmic cube," Communications of the ACM, vol. 28, no. 1, pp. 22--33, ACM, January 1985.

Digital Library

[13]

Walt87. David L. Waltz, "Applications of the Connection Machine," Computer, vol. 20, no. 1, pp. 85--97, IEEE, January 1987.

Digital Library

[14]

Fish81. Joseph A. Fisher, "Trace Scheduling: A technique for global microcode compaction," Transactions on Computers, vol. C-30, pp. 478--490, IEEE, July, 1981.

[15]

Fish84. Joseph A. Fisher and John J. O'Donnell, "VLIW Machines: Multiprocessors We Can Actually Program," CompCon 84 Proceedings, pp. 299--305, IEEE, 1984.

[16]

Elli84.John R. Ellis, Joseph A. Fisher, John C. Ruttenberg, and Alexandru Nicolau, "Parallel Processing: A Smart Compiler and a Dumb Machine," Proceedings of the SIGPLAN 84 Symposium on Compiler Construction, ACM SIGPLAN Notices, June 1984.

Digital Library

[17]

Pfis85.Gregory F. Pfister and V. Alan Norton, "Hot-Spot Contention and Combining in Multistage Interconnection Networks," Transactions on Computers, vol. C-34, pp. 943--948, IEEE, October 1985.

[18]

Smit82. Alan Jay Smith, "Cache Memories," ACM Computing Surveys, ACM, September 1982.

[19]

Clar85. Douglas W. Clark and Joel S. Emer, "Performance of the VAX-11/780 Translation Buffer: Simulation and Measurement," ACM Transactions on Computer Systems, vol. 3, no. 1, pp. 31--62, February 1985.

Digital Library

[20]

Wall86. David W. Wall, "Global Register Allocation at Link Time," Proceedings of the SIGPLAN 86 Symposium on Compiler Construction, ACM SIGPLAN Notices, July 1986.

Digital Library

Cited By

AlFayez F(2023)Algorithms for Pre-Compiling Programs by Parallel CompilersComputer Systems Science and Engineering10.32604/csse.2023.02623844:3(2165-2176)Online publication date: 2023
https://doi.org/10.32604/csse.2023.026238
Bhagyanath ASchneider KTalpin J(2016)Optimal compilation for exposed datapath architectures with buffered processing units by SAT solversProceedings of the 14th ACM-IEEE International Conference on Formal Methods and Models for System Design10.5555/3343414.3343435(143-152)Online publication date: 18-Nov-2016
https://dl.acm.org/doi/10.5555/3343414.3343435
Gupta MSanchez FLlosa J(2010)CSMTIEEE Transactions on Computers10.1109/TC.2009.9659:3(385-399)Online publication date: 1-Mar-2010
https://dl.acm.org/doi/10.1109/TC.2009.96
Show More Cited By

Index Terms

A VLIW architecture for a trace scheduling compiler

Recommendations

A VLIW architecture for a trace Scheduling Compiler
Special issue on architectural support for programming languages and operating systems

A VLIW (very long instruction word) architecture machine called the TRACE has been built along with its companion Trace Scheduling compacting compiler. This machine has three hardware configurations, capable of executing 7, 14, or 28 operations ...
A VLIW architecture for a trace scheduling compiler

Very Long Instruction Word (VLIW) architectures were promised to deliver far more than the factor of two or three that current architectures achieve from overlapped execution. Using a new type of compiler which compacts ordinary sequential code into ...
A VLIW architecture for a trace scheduling compiler
ASPLOS II: Proceedings of the second international conference on Architectual support for programming languages and operating systems

Very Long Instruction Word (VLIW) architectures were promised to deliver far more than the factor of two or three that current architectures achieve from overlapped execution. Using a new type of compiler which compacts ordinary sequential code into ...

Comments

Please enable JavaScript to view thecomments powered by Disqus.

Information & Contributors

Information

Published In

cover image ACM SIGARCH Computer Architecture News

ACM SIGARCH Computer Architecture News Volume 15, Issue 5

Oct. 1987

189 pages

ISSN:0163-5964

DOI:10.1145/36177

Editor:
Randy H. Katz
Univ. of California, Berkeley

Issue’s Table of Contents

ASPLOS II: Proceedings of the second international conference on Architectual support for programming languages and operating systems
October 1987
205 pages
ISBN:0818608056
DOI:10.1145/36206
Editor:
Randy Katz
Univ. of California, Berkeley
,
General Chair:
Martin Freeman
Stanford University and Philips/Signetics

Copyright © 1987 Copyright is held by the owner/author(s).

Permission to make digital or hard copies of part or all of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for third-party components of this work must be honored. For all other uses, contact the Owner/Author.

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 01 October 1987

Published in SIGARCH Volume 15, Issue 5

Check for updates

Qualifiers

Article

Contributors

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

109
Total Citations
View Citations
2,621
Total Downloads

Downloads (Last 12 months)466
Downloads (Last 6 weeks)55

Reflects downloads up to 18 Dec 2024

Other Metrics

View Author Metrics

Citations

Cited By

AlFayez F(2023)Algorithms for Pre-Compiling Programs by Parallel CompilersComputer Systems Science and Engineering10.32604/csse.2023.02623844:3(2165-2176)Online publication date: 2023
https://doi.org/10.32604/csse.2023.026238
Bhagyanath ASchneider KTalpin J(2016)Optimal compilation for exposed datapath architectures with buffered processing units by SAT solversProceedings of the 14th ACM-IEEE International Conference on Formal Methods and Models for System Design10.5555/3343414.3343435(143-152)Online publication date: 18-Nov-2016
https://dl.acm.org/doi/10.5555/3343414.3343435
Gupta MSanchez FLlosa J(2010)CSMTIEEE Transactions on Computers10.1109/TC.2009.9659:3(385-399)Online publication date: 1-Mar-2010
https://dl.acm.org/doi/10.1109/TC.2009.96
Whitham JAudsley N(2006)MCGREP--A Predictable Architecture for Embedded Real-Time SystemsProceedings of the 27th IEEE International Real-Time Systems Symposium10.1109/RTSS.2006.28(13-24)Online publication date: 5-Dec-2006
https://dl.acm.org/doi/10.1109/RTSS.2006.28
Lewis D(2006)A compiled-code hardware accelerator for circuit simulationIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/43.12761711:5(555-565)Online publication date: 1-Nov-2006
https://dl.acm.org/doi/10.1109/43.127617
Chen SFuchs W(2001)Compiler-Assisted Multiple Instruction Word Retry for VLIW ArchitecturesIEEE Transactions on Parallel and Distributed Systems10.1109/71.97056412:12(1293-1304)Online publication date: 1-Dec-2001
https://dl.acm.org/doi/10.1109/71.970564
Cascaval CDeRose LPadua DReed D(2001)Compile-Time Based Performance PredictionLanguages and Compilers for Parallel Computing10.1007/3-540-44905-1_23(365-379)Online publication date: 12-Jun-2001
https://doi.org/10.1007/3-540-44905-1_23
Schmit HCadambi SMoe MGoldstein S(2000)Pipeline Reconfigurable FPGAsField-Programmable Custom Computing Technology: Architectures, Tools, and Applications10.1007/978-1-4615-4417-3_2(3-20)Online publication date: 2000
https://doi.org/10.1007/978-1-4615-4417-3_2
Ozer EBanerjia SConte T(1998)Unified assign and schedule: a new approach to scheduling for clustered register file microarchitecturesProceedings. 31st Annual ACM/IEEE International Symposium on Microarchitecture10.1109/MICRO.1998.742792(308-315)Online publication date: 1998
https://doi.org/10.1109/MICRO.1998.742792
Rathman SSlavenburg G(1998)Processing the new world of interactive mediaIEEE Signal Processing Magazine10.1109/79.66470415:2(108-117)Online publication date: Mar-1998
https://doi.org/10.1109/79.664704
Show More Cited By

View Options

View options

PDF

View or Download as a PDF file.

eReader

View online with eReader.

Login options

Check if you have access through your login credentials or your institution to get full access on this article.

Full Access

Get this Publication

Media

Figures

Other

Tables

View Issue’s Table of Contents