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Tai Song
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2020 – today
- 2024
- [j15]Zhengfeng Huang
, Yan Zhang
Designs of High-Speed Triple-Node-Upset Hardened Latch Based on Dual-Modular-Redundancy. J. Circuits Syst. Comput. 33(5): 2450092:1-2450092:25 (2024) - [j14]Hui Xu, Chaoming Liu, Ruijun Ma
Hardened latch designs based on the characteristic of transistor for mitigating multiple-node-upsets in harsh radiation environments. Microelectron. J. 143: 106031 (2024) - [j13]Tai Song
Test Cost Reduction for VLSI Adaptive Test With K-Nearest Neighbor Classification Algorithm. IEEE Trans. Circuits Syst. II Express Briefs 71(7): 3508-3512 (2024) - 2023
- [j12]Tai Song
Cost-Effective Path Delay Defect Testing Using Voltage/Temperature Analysis Based on Pattern Permutation. J. Electron. Test. 39(2): 189-205 (2023) - [j11]Liang Huang, Tai Song
Linear regression combined KNN algorithm to identify latent defects for imbalance data of ICs. Microelectron. J. 131: 105641 (2023) - [j10]Zhengfeng Huang
Overhead Optimized and Quadruple-Node-Upset Self-Recoverable Latch Design Based on Looped C-Element Matrix. IEEE Trans. Aerosp. Electron. Syst. 59(6): 9357-9367 (2023) - 2022
- [j9]Tai Song
Valid test pattern identification for VLSI adaptive test. Integr. 82: 1-6 (2022) - [j8]Aibin Yan, Kuikui Qian, Tai Song, Zhengfeng Huang, Tianming Ni, Yu Chen, Xiaoqing Wen:
A double-node-upset completely tolerant CMOS latch design with extremely low cost for high-performance applications. Integr. 86: 22-29 (2022) - [j7]Tai Song
Machine learning classification algorithm for VLSI test cost reduction. Integr. 87: 40-48 (2022) - [j6]Zhengfeng Huang, Wanshu Zhong, Lanxi Duan, Yue Zhang, Huaguo Liang, Jianan Wang, Tai Song, Yingchun Lu:
Low-Power Anti-Glitch Double-Edge Triggered Flip-Flop Based on Robust C-Elements. J. Circuits Syst. Comput. 31(13): 2250231:1-2250231:17 (2022) - [j5]Liang Huang, Tai Song
VLSI test through an improved LDA classification algorithm for test cost reduction. Microelectron. J. 125: 105461 (2022) - [j4]Tai Song
RLDA: Valid test pattern identification by machine learning classification method for VLSI test. Microelectron. J. 128: 105549 (2022) - 2021
- [j3]Tai Song
Chip test pattern reordering method using adaptive test to reduce cost for testing of ICs. IEICE Electron. Express 18(2): 20200420 (2021) - 2020
- [j2]Tai Song
Pattern Reorder for Test Cost Reduction Through Improved SVMRANK Algorithm. IEEE Access 8: 147965-147972 (2020) - [j1]Tianming Ni
Non-Intrusive Online Distributed Pulse Shrinking-Based Interconnect Testing in 2.5D IC. IEEE Trans. Circuits Syst. 67-II(11): 2657-2661 (2020)
2010 – 2019
- 2019
- [c1]Tai Song
Novel Application of Deep Learning for Adaptive Testing Based on Long Short-Term Memory. VTS 2019: 1-6
Coauthor Index
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