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Yasuo Sato
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2020 – today
- 2020
- [j14]Gian Mayuga
, Yasuo Sato, Michiko Inoue
Highly Reliable Memory Architecture Using Adaptive Combination of Proactive Aging-Aware In-Field Self-Repair and ECC. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(8): 1688-1698 (2020) - [j13]Takaaki Kato
A Flexible Scan-in Power Control Method in Logic BIST and Its Evaluation with TEG Chips. IEEE Trans. Emerg. Top. Comput. 8(3): 591-601 (2020)
2010 – 2019
- 2019
- [c52]Yousuke Miyake
A Selection Method of Ring Oscillators for An On-Chip Digital Temperature And Voltage Sensor. ITC-Asia 2019: 13-18 - [c51]Yousuke Miyake
On-Chip Delay Measurement for In-Field Test of FPGAs. PRDC 2019: 130-137 - 2018
- [c50]Shigeyuki Oshima, Takaaki Kato, Senling Wang, Yasuo Sato, Seiji Kajihara:
On Flip-Flop Selection for Multi-cycle Scan Test with Partial Observation in Logic BIST. ATS 2018: 30-35 - [c49]Takeru Nishimi, Yasuo Sato, Seiji Kajihara, Yoshiyuki Nakamura:
Good Die Prediction Modelling from Limited Test Items. ITC-Asia 2018: 115-120 - 2017
- [c48]Yousuke Miyake
On the effects of real time and contiguous measurement with a digital temperature and voltage sensor. ITC-Asia 2017: 125-130 - 2016
- [j12]Gian Mayuga, Yuta Yamato, Tomokazu Yoneda, Yasuo Sato, Michiko Inoue:
Reliability-Enhanced ECC-Based Memory Architecture Using In-Field Self-Repair. IEICE Trans. Inf. Syst. 99-D(10): 2591-2599 (2016) - [j11]Yousuke Miyake
Temperature and Voltage Measurement for Field Test Using an Aging-Tolerant Monitor. IEEE Trans. Very Large Scale Integr. Syst. 24(11): 3282-3295 (2016) - [c47]Takaaki Kato, Senling Wang, Yasuo Sato, Seiji Kajihara, Xiaoqing Wen:
A Flexible Power Control Method for Right Power Testing of Scan-Based Logic BIST. ATS 2016: 203-208 - [c46]Gian Mayuga, Yuta Yamato, Tomokazu Yoneda, Yasuo Sato, Michiko Inoue:
Reliability enhancement of embedded memory with combination of aging-aware adaptive in-field self-repair and ECC. ETS 2016: 1-2 - 2015
- [j10]Senling Wang, Yasuo Sato, Seiji Kajihara, Hiroshi Takahashi:
Physical Power Evaluation of Low Power Logic-BIST Scheme Using Test Element Group Chip. J. Low Power Electron. 11(4): 528-540 (2015) - [c45]Gian Mayuga, Yuta Yamato, Tomokazu Yoneda, Michiko Inoue, Yasuo Sato:
An ECC-based memory architecture with online self-repair capabilities for reliability enhancement. ETS 2015: 1-6 - 2014
- [j9]Akihiro Tomita, Xiaoqing Wen, Yasuo Sato, Seiji Kajihara, Kohei Miyase, Stefan Holst, Patrick Girard, Mohammad Tehranipoor, Laung-Terng Wang:
On Achieving Capture Power Safety in At-Speed Scan-Based Logic BIST. IEICE Trans. Inf. Syst. 97-D(10): 2706-2718 (2014) - [c44]Yousuke Miyake
Temperature and Voltage Estimation Using Ring-Oscillator-Based Monitor for Field Test. ATS 2014: 156-161 - [c43]Seiji Kajihara, Yousuke Miyake
An On-Chip Digital Environment Monitor for Field Test. ATS 2014: 254-257 - [c42]Yasuo Sato, Masafumi Monden, Yousuke Miyake
Reduction of NBTI-Induced Degradation on Ring Oscillators in FPGA. PRDC 2014: 59-67 - 2013
- [j8]Senling Wang
Scan-Out Power Reduction for Logic BIST. IEICE Trans. Inf. Syst. 96-D(9): 2012-2020 (2013) - [c41]Akihiro Tomita, Xiaoqing Wen, Yasuo Sato, Seiji Kajihara, Patrick Girard, Mohammad Tehranipoor, Laung-Terng Wang:
On Achieving Capture Power Safety in At-Speed Scan-Based Logic BIST. Asian Test Symposium 2013: 19-24 - [c40]Yasuo Sato, Seiji Kajihara:
A Stochastic Model for NBTI-Induced LSI Degradation in Field. Asian Test Symposium 2013: 183-188 - 2012
- [j7]Hyunbean Yi, Tomokazu Yoneda, Michiko Inoue, Yasuo Sato, Seiji Kajihara, Hideo Fujiwara:
A Failure Prediction Strategy for Transistor Aging. IEEE Trans. Very Large Scale Integr. Syst. 20(11): 1951-1959 (2012) - [c39]Yasuo Sato, Senling Wang, Takaaki Kato, Kohei Miyase, Seiji Kajihara:
Low Power BIST for Scan-Shift and Capture Power. Asian Test Symposium 2012: 173-178 - [c38]Senling Wang, Yasuo Sato, Kohei Miyase, Seiji Kajihara:
A Scan-Out Power Reduction Method for Multi-cycle BIST. Asian Test Symposium 2012: 272-277 - [c37]Yukiya Miura, Yasuo Sato, Yousuke Miyake
On-chip temperature and voltage measurement for field testing. ETS 2012: 1 - [c36]Yasuo Sato, Seiji Kajihara, Tomokazu Yoneda, Kazumi Hatayama, Michiko Inoue, Yukiya Miura, Satosni Untake, Takumi Hasegawa, Motoyuki Sato, Kotaro Shimamura:
DART: Dependable VLSI test architecture and its implementation. ITC 2012: 1-10 - 2011
- [c35]Yasuo Sato, Hisato Yamaguchi, Makoto Matsuzono, Seiji Kajihara:
Multi-cycle Test with Partial Observation on Scan-Based BIST Structure. Asian Test Symposium 2011: 54-59 - [c34]Xiaoxin Fan, Sudhakar M. Reddy, Senling Wang, Seiji Kajihara, Yasuo Sato:
Genetic algorithm based approach for segmented testing. DSN Workshops 2011: 85-90 - [c33]Tomokazu Yoneda, Makoto Nakao, Michiko Inoue, Yasuo Sato, Hideo Fujiwara:
Temperature-Variation-Aware Test Pattern Optimization. ETS 2011: 214 - [c32]Yasuo Sato:
Special session: Multifaceted approaches for field reliability. VTS 2011: 96 - 2010
- [j6]Shinji Oku, Seiji Kajihara, Yasuo Sato, Kohei Miyase, Xiaoqing Wen:
On Delay Test Quality for Test Cubes. Inf. Media Technol. 5(4): 1147-1155 (2010) - [j5]Shinji Oku, Seiji Kajihara, Yasuo Sato, Kohei Miyase, Xiaoqing Wen:
On Delay Test Quality for Test Cubes. IPSJ Trans. Syst. LSI Des. Methodol. 3: 283-291 (2010) - [c31]Yasuo Sato:
Circuit Failure Prediction by Field Test - A New Task of Testing. DFT 2010: 69-70 - [c30]Mitsumasa Noda, Seiji Kajihara, Yasuo Sato, Kohei Miyase, Xiaoqing Wen, Yukiya Miura:
On estimation of NBTI-Induced delay degradation. ETS 2010: 107-111 - [c29]Hyunbean Yi, Tomokazu Yoneda, Michiko Inoue, Yasuo Sato, Seiji Kajihara, Hideo Fujiwara:
Aging test strategy and adaptive test scheduling for SoC failure prediction. IOLTS 2010: 21-26 - [c28]Tomokazu Yoneda, Michiko Inoue, Yasuo Sato, Hideo Fujiwara:
Thermal-uniformity-aware X-filling to reduce temperature-induced delay variation for accurate at-speed testing. VTS 2010: 188-193
2000 – 2009
- 2008
- [j4]Hiroshi Takahashi, Yoshinobu Higami, Shuhei Kadoyama, Yuzo Takamatsu, Koji Yamazaki, Takashi Aikyo, Yasuo Sato:
Post-BIST Fault Diagnosis for Multiple Faults. IEICE Trans. Inf. Syst. 91-D(3): 771-775 (2008) - 2007
- [c27]Yasuharu Kohiyama, C. P. Ravikumar, Yasuo Sato, Laung-Terng Wang, Yervant Zorian:
Next Generation Test, Diagnostics and Yield Challenges for EDA, ATE, IP and Fab - A Perspective from All Sides. ATS 2007: 207 - 2006
- [j3]Yasuo Sato, Shuji Hamada, Toshiyuki Maeda, Atsuo Takatori, Seiji Kajihara:
A Statistical Quality Model for Delay Testing. IEICE Trans. Electron. 89-C(3): 349-355 (2006) - [c26]Masayasu Fukunaga, Seiji Kajihara, Xiaoqing Wen, Toshiyuki Maeda, Shuji Hamada, Yasuo Sato:
A dynamic test compaction procedure for high-quality path delay testing. ASP-DAC 2006: 348-353 - [c25]Xijiang Lin, Kun-Han Tsai, Chen Wang, Mark Kassab, Janusz Rajski, Takeo Kobayashi, Randy Klingenberg, Yasuo Sato, Shuji Hamada, Takashi Aikyo:
Timing-Aware ATPG for High Quality At-speed Testing of Small Delay Defects. ATS 2006: 139-146 - [c24]Anis Uzzaman, Mick Tegethoff, Bibo Li, Kevin McCauley, Shuji Hamada, Yasuo Sato:
Not all Delay Tests Are the Same - SDQL Model Shows True-Time. ATS 2006: 147-152 - [c23]Dhiraj Goswami, Kun-Han Tsai, Mark Kassab, Takeo Kobayashi, Janusz Rajski, Bruce Swanson, Darryl Walters, Yasuo Sato, Toshiharu Asaka, Takashi Aikyo:
At-Speed Testing with Timing Exceptions and Constraints-Case Studies. ATS 2006: 153-162 - [c22]Yasuo Sato, Kazushi Sugiura, Reisuke Shimoda, Yutaka Yoshizawa, Kenji Norimatsu, Masaru Sanada:
Defect Diagnosis - Reasoning Methodology. ATS 2006: 209-214 - [c21]Hiroshi Takahashi, Shuhei Kadoyama, Yoshinobu Higami, Yuzo Takamatsu, Koji Yamazaki, Takashi Aikyo, Yasuo Sato:
Effective Post-BIST Fault Diagnosis for Multiple Faults. DFT 2006: 401-109 - [c20]Shuji Hamada, Toshiyuki Maeda, Atsuo Takatori, Yasuyuki Noduyama, Yasuo Sato:
Recognition of Sensitized Longest Paths in Transition Delay Test. ITC 2006: 1-6 - [c19]Seiji Kajihara, Shohei Morishima, Akane Takuma, Xiaoqing Wen, Toshiyuki Maeda, Shuji Hamada, Yasuo Sato:
A Framework of High-quality Transition Fault ATPG for Scan Circuits. ITC 2006: 1-6 - 2005
- [c18]Yasuo Sato, Shuji Hamada, Toshiyuki Maeda, Atsuo Takatori, Seiji Kajihara:
Evaluation of the statistical delay quality model. ASP-DAC 2005: 305-310 - [c17]Seiji Kajihara, Masayasu Fukunaga, Xiaoqing Wen, Toshiyuki Maeda, Shuji Hamada, Yasuo Sato:
Path delay test compaction with process variation tolerance. DAC 2005: 845-850 - [c16]Yasuo Sato, Shuji Hamada, Toshiyuki Maeda, Atsuo Takatori, Yasuyuki Nozuyama, Seiji Kajihara:
Invisible delay quality - SDQM model lights up what could not be seen. ITC 2005: 9 - 2004
- [j2]Yasuo Sato, Iwao Yamazaki, Hiroki Yamanaka, Toshio Ikeda, Masahiro Takakura, Kazuhiko Iwasaki:
Technique to Diagnose Open Defects that Takes Coupling Effects into Consideration. IEICE Trans. Inf. Syst. 87-D(9): 2179-2185 (2004) - 2003
- [j1]Yasuo Sato, Motoyuki Sato, Koki Tsutsumida, Kazumi Hatayama, Kazuyuki Nomoto:
DFT Timing Design Methodology for Logic BIST. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 86-A(12): 3049-3055 (2003) - [c15]Yasuo Sato, Motoyuki Sato, Koki Tsutsumida, Masatoshi Kawashima, Kazumi Hatayama, Kazuyuki Nomoto:
DFT timing design methodology for at-speed BIST. ASP-DAC 2003: 763-768 - 2002
- [c14]Kazumi Hatayama, Michinobu Nakao, Yasuo Sato:
At-Speed Built-in Test for Logic Circuits with Multiple Clocks. Asian Test Symposium 2002: 292-297 - [c13]Yasuo Sato, Iwao Yamazaki, Hiroki Yamanaka, Toshio Ikeda, Masahiro Takakura:
A Persistent Diagnostic Technique for Unstable Defects. ITC 2002: 242-249 - [c12]Kazumi Hatayama, Michinobu Nakao, Yoshikazu Kiyoshige, Koichiro Natsume, Yasuo Sato, Takaharu Nagumo:
Application of High-Quality Built-In Test to Industrial Designs. ITC 2002: 1003-1012 - 2001
- [c11]Iwao Yamazaki, Hiroki Yamanaka, Toshio Ikeda, Masahiro Takakura, Yasuo Sato:
An Approach to Improve the Resolution of Defect-Based Diagnosis. Asian Test Symposium 2001: 123- - [c10]Michinobu Nakao, Yoshikazu Kiyoshige, Kazumi Hatayama, Yasuo Sato, Takaharu Nagumo:
Test Generation for Multiple-Threshold Gate-Delay Fault Model. Asian Test Symposium 2001: 244- - [c9]Yasuo Sato, Motoyuki Sato, Koki Tsutsumida, Toyohito Ikeya, Masatoshi Kawashima:
A Practical Logic BIST for ASIC Designs. Asian Test Symposium 2001: 457 - [c8]Yasuo Sato, Masaki Kohno, Toshio Ikeda, Iwao Yamazaki, Masato Hamamoto:
An evaluation of defect-oriented test: WELL-controlled low voltage test. ITC 2001: 1059-1067 - 2000
- [c7]Yasuo Sato, Toyohito Ikeya, Michinobu Nakao, Takaharu Nagumo:
A BIST approach for very deep sub-micron (VDSM) defects. ITC 2000: 283-291
1990 – 1999
- 1996
- [c6]Yasuo Sato, Michiko Inoue, Toshimitsu Masuzawa, Hideo Fujiwara:
A Snapshot Algorithm for Distributed Mobile Systems. ICDCS 1996: 734-743 - 1991
- [c5]Yasushi Ogawa, Tsutomu Itoh, Yoshio Miki, Tatsuki Ishii, Yasuo Sato, Reiji Toyoshima:
Timing- and Constraint-Oriented Placement for Interconnected LSIs in Mainframe Design. DAC 1991: 253-258
1980 – 1989
- 1986
- [c4]Koji Tajima, Mitsuo Komura, Yasuo Sato:
Connected word recognition by overlap and split of reference patterns and its performance evaluation tests. ICASSP 1986: 1101-1104 - 1984
- [c3]Hynek Hermansky, Hiroya Fujisaki, Yasuo Sato:
Spectral envelope sampling and interpolation in linear predictive analysis of speech. ICASSP 1984: 53-56 - [c2]Hiroya Fujisaki, Keikichi Hirose, Tomohiro Inoue, Yasuo Sato:
Automatic recognition of spoken words from a large vocabulary using syllable templates. ICASSP 1984: 605-608 - 1983
- [c1]Hynek Hermansky, Hiroya Fujisaki, Yasuo Sato:
Analysis and synthesis of speech based on spectral transform linear predictive method. ICASSP 1983: 777-780
Coauthor Index
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