Article

Evaluation of the statistical delay quality model

Authors:

Seiji KajiharaAuthors Info & Claims

ASP-DAC '05: Proceedings of the 2005 Asia and South Pacific Design Automation Conference

Pages 305 - 310

https://doi.org/10.1145/1120725.1120856

Published: 18 January 2005 Publication History

Get Access

Abstract

In this paper we introduce a quality model that reflects fabrication process quality, design delay margin, and test timing accuracy. The model provides a measure that can predict the level of chip defects that cause delay failure, including marginal delay. We can therefore use the model to make test vectors that are effective in terms of both testing cost and chip quality. The results of experiments using ISCAS89 benchmark data and some large industrial design data reflect various characteristics of our statistical delay quality model.

References

[1]

A. Krstic and K. T. Cheng, "Delay fault testing for VLSI circuits," Kluwer Academic Publishers, Norwell, MA, 1998.

Google Scholar

[2]

K. Yang, K. T. Cheng, and L. C. Wang, "TranGen: a SAT-based atpg for path-oriented transition faults," Proc. Asian and South Pacific Design Automation Conference, pp. 92--97, Jan. 2004.

Digital Library

Google Scholar

[3]

J. Savir, "On broad-side delay testing," Proc. IEEE VLSI Test Symposium, pp. 284--290, 1994.

Crossref

Google Scholar

[4]

G. Hetherington, T. Fryars, N. Tamarapalli, M. Kassab, A. Hassan, and J. Rajski, "Logic BIST for large industrial designs: real issues and case studies," Proc. IEEE International Test Conference, pp. 358--367, 1999.

Digital Library

Google Scholar

[5]

B. N. Dostie, "Design for at-speed test, diagnosis and measurement," Kluwer Academic Publishers, Boston, MA, 1999.

Google Scholar

[6]

Y. Sato, M. Sato, K. Tsutsumida, M. Kawashima, K. Hatayama, and K. Nomoto, "DFT timing design methodology for at-speed BIST," Proc. Asian and South Pacific Design Automation Conference, pp. 763--768, Jan. 2003.

Digital Library

Google Scholar

[7]

E. S. Park, M. R. Mercer, and T. W. Williams, "Statistical delay fault coverage and defect level for delay faults," Proc. IEEE International Test Conference, pp. 160--167, 1988.

Google Scholar

[8]

E. S. Park, B. Underwood, T. W. Williams, and M. R. Mercer, "Delay testing quality in timing-optimized designs," Proc. IEEE International Test Conference, pp. 168--176, 1991

Digital Library

Google Scholar

[9]

P. Nigh and A. Gattiker, "Test method evaluation experiments & data," Proc. IEEE International Test Conference, pp. 454--463, 2000.

Digital Library

Google Scholar

[10]

D. M. Wu and C. E. Radke, "Delay test effectiveness evaluation of LSSD-based VLSI logic circuits," Proc. ACM/IEEE Design Automation Conference, pp. 291--295, Jun. 1991.

Digital Library

Google Scholar

[11]

V. S. Iyengar, B. K. Rosen, and J. A. Waicukauski, "On computing the sizes of detected delay faults," IEEE Trans. on Comput.-Aided Des. Integr. Circuits Syst., pp. 299--312, Mar. 1990.

Digital Library

Google Scholar

[12]

M. Nakao, Y. Kiyoshige, K. Hatayama, Y. Sato, and T. Nagumo, "Test generation for multiple-threshold gate-delay fault model," Proc. Asian Test Symposium, pp. 244--249, Nov. 2001.

Digital Library

Google Scholar

[13]

M. Fukunaga, S. Kajihara, S. Takeoka, and S. Yosimura, "On effective criterion of path selection for delay testing," Proc. Asian and South Pacific Design Automation Conference, pp. 757--762, 2003.

Digital Library

Google Scholar

[14]

C. W. Tseng, J. Li, and E. D. McCluskey, "Experimental results for slow-speed testing," Proc. IEEE VLSI Test Symposium, pp. 37--42, 2002.

Digital Library

Google Scholar

Cited By

View all

Basu KSaeed SPilato CAshraf MNabeel MChakrabarty KKarri R(2019)CAD-BaseACM Transactions on Design Automation of Electronic Systems10.1145/331557424:4(1-30)Online publication date: 18-Apr-2019
https://dl.acm.org/doi/10.1145/3315574
Liu YHan CLin SLi J(2017)PSN‐aware circuit test timing prediction using machine learningIET Computers & Digital Techniques10.1049/iet-cdt.2016.003211:2(60-67)Online publication date: 25-Jan-2017
https://doi.org/10.1049/iet-cdt.2016.0032
García-Gervacio JNocua AChampac V(2015)Screening small-delay defects using inter-path correlation to reduce reliability riskMicroelectronics Reliability10.1016/j.microrel.2015.03.00755:6(1005-1011)Online publication date: May-2015
https://doi.org/10.1016/j.microrel.2015.03.007
Show More Cited By

Evaluation of the statistical delay quality model
1. Computer systems organization
2. Hardware

Recommendations

The Total Delay Fault Model and Statistical Delay Fault Coverage

Delay testing at the operational system clock rate can detect system timing failures caused by delay faults. However, delay fault coverage in terms of the percentage of the number of tested faults may not be an effective measure of delay testing. A ...
A Statistical Model for Delay-Fault Testing

The authors propose a statistical model for measuring delay-fault coverage. The model provides a figure of merit for delay testing in the same way that fault coverage provides one for the testing of single stuck-at faults. The mode measures test ...
Statistical delay fault coverage and defect level for delay faults
ITC'88: Proceedings of the 1988 international conference on Test: new frontiers in testing

This paper presents a quantitative delay fault coverage model to provide a figure of merit for delay testing. System sensitivity of a path to a delay fault along that path and the effectiveness of a delay test are described in terms of the propagation ...

Comments

Please enable JavaScript to view thecomments powered by Disqus.

Information & Contributors

Information

Published In

ASP-DAC '05: Proceedings of the 2005 Asia and South Pacific Design Automation Conference

January 2005

1495 pages

ISBN:0780387376

DOI:10.1145/1120725

General Chair:
Ting-Ao Tang
Fudan University, Shanghai, P. R. China

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 18 January 2005

Permissions

Request permissions for this article.

Request Permissions

Check for updates

Qualifiers

Article

Conference

ASPDAC05

Sponsor:

SIGDA

ASPDAC05: Asia and South Pacific Design Automation Conference

January 18 - 21, 2005

Shanghai, China

Acceptance Rates

Overall Acceptance Rate 466 of 1,454 submissions, 32%

Upcoming Conference

ASPDAC '25

Sponsor:
sigda

30th Asia and South Pacific Design Automation Conference

January 20 - 23, 2025

Tokyo , Japan

Contributors

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

11
Total Citations
View Citations
292
Total Downloads

Downloads (Last 12 months)1
Downloads (Last 6 weeks)0

Reflects downloads up to 13 Dec 2024

Other Metrics

View Author Metrics

Citations

Cited By

View all

Basu KSaeed SPilato CAshraf MNabeel MChakrabarty KKarri R(2019)CAD-BaseACM Transactions on Design Automation of Electronic Systems10.1145/331557424:4(1-30)Online publication date: 18-Apr-2019
https://dl.acm.org/doi/10.1145/3315574
Liu YHan CLin SLi J(2017)PSN‐aware circuit test timing prediction using machine learningIET Computers & Digital Techniques10.1049/iet-cdt.2016.003211:2(60-67)Online publication date: 25-Jan-2017
https://doi.org/10.1049/iet-cdt.2016.0032
García-Gervacio JNocua AChampac V(2015)Screening small-delay defects using inter-path correlation to reduce reliability riskMicroelectronics Reliability10.1016/j.microrel.2015.03.00755:6(1005-1011)Online publication date: May-2015
https://doi.org/10.1016/j.microrel.2015.03.007
Liu TKuang JCai SYou Z(2014)An efficient small‐delay faults simulator based on critical path tracingInternational Journal of Circuit Theory and Applications10.1002/cta.199043:8(1015-1023)Online publication date: 16-Apr-2014
https://doi.org/10.1002/cta.1990
Ho SLin SYuan KKuo CLiao KJiang JLi CHenkel J(2013)Automatic test pattern generation for delay defects using timed characteristic functionsProceedings of the International Conference on Computer-Aided Design10.5555/2561828.2561848(91-98)Online publication date: 18-Nov-2013
https://dl.acm.org/doi/10.5555/2561828.2561848
INOUE MTAKETANI AYONEDA TFUJIWARA H(2012)Test Pattern Ordering and Selection for High Quality Test Set under ConstraintsIEICE Transactions on Information and Systems10.1587/transinf.E95.D.3001E95.D:12(3001-3009)Online publication date: 2012
https://doi.org/10.1587/transinf.E95.D.3001
Yoneda TInoue MTaketani AFujiwara H(2010)Seed Ordering and Selection for High Quality Delay TestProceedings of the 2010 19th IEEE Asian Test Symposium10.1109/ATS.2010.60(313-318)Online publication date: 1-Dec-2010
https://dl.acm.org/doi/10.1109/ATS.2010.60
Kajihara SOku SMiyase KWen XSato Y(2009)On calculation of delay range in fault simulation for test cubes2009 International Symposium on VLSI Design, Automation and Test10.1109/VDAT.2009.5158096(64-67)Online publication date: Apr-2009
https://doi.org/10.1109/VDAT.2009.5158096
Chen MOrailoglu A(2009)Flip-Flop Hardening and Selection for Soft Error and Delay Fault ResilienceProceedings of the 2009 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems10.1109/DFT.2009.50(49-57)Online publication date: 7-Oct-2009
https://dl.acm.org/doi/10.1109/DFT.2009.50
Reddy S(2009)Models for Delay FaultsModels in Hardware Testing10.1007/978-90-481-3282-9_3(71-103)Online publication date: 27-Oct-2009
https://doi.org/10.1007/978-90-481-3282-9_3
Show More Cited By

View Options

Login options

Check if you have access through your login credentials or your institution to get full access on this article.

Cited By

Recommendations

The Total Delay Fault Model and Statistical Delay Fault Coverage

A Statistical Model for Delay-Fault Testing

Statistical delay fault coverage and defect level for delay faults