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Farimah Farahmandi
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2020 – today
- 2024
- [j31]Md Sami Ul Islam Sami
, Tao Zhang
Advancing Trustworthiness in System-in-Package: A Novel Root-of-Trust Hardware Security Module for Heterogeneous Integration. IEEE Access 12: 48081-48107 (2024) - [j30]Dipayan Saha
LLM for SoC Security: A Paradigm Shift. IEEE Access 12: 155498-155521 (2024) - [j29]Muhammad Monir Hossain
Fuzzing for Automated SoC Security Verification: Challenges and Solution. IEEE Des. Test 41(4): 7-16 (2024) - [j28]Mridha Md Mashahedur Rahman
Efficient SoC Security Monitoring: Quality Attributes and Potential Solutions. IEEE Des. Test 41(4): 26-34 (2024) - [j27]Mridha Md Mashahedur Rahman
The Road Not Taken: eFPGA Accelerators Utilized for SoC Security Auditing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 43(10): 3068-3082 (2024) - [j26]Avinash Ayalasomayajula
Automatic Asset Identification for Assertion-Based SoC Security Verification. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 43(10): 3264-3277 (2024) - [j25]Nusrat Farzana Dipu
AGILE: Automated Assertion Generation to Detect Information Leakage Vulnerabilities. IEEE Trans. Inf. Forensics Secur. 19: 1794-1809 (2024) - [j24]Kimia Zamiri Azar, Hadi Mardani Kamali
Improving Bounded Model Checkers Scalability for Circuit De-Obfuscation: An Exploration. IEEE Trans. Inf. Forensics Secur. 19: 2771-2785 (2024) - [j23]Sree Ranjani Rajendran
Exploring the Abyss? Unveiling Systems-on-Chip Hardware Vulnerabilities Beneath Software. IEEE Trans. Inf. Forensics Secur. 19: 3914-3926 (2024) - [j22]Paul Calzada
Heterogeneous Integration Supply Chain Integrity Through Blockchain and CHSM. ACM Trans. Design Autom. Electr. Syst. 29(1): 9:1-9:25 (2024) - [j21]Tao Zhang
SiPGuard: Run-Time System-in-Package Security Monitoring via Power Noise Variation. IEEE Trans. Very Large Scale Integr. Syst. 32(2): 305-318 (2024) - [j20]Tao Zhang
TrustGuard: Standalone FPGA-Based Security Monitoring Through Power Side-Channel. IEEE Trans. Very Large Scale Integr. Syst. 32(2): 319-332 (2024) - [j19]Amit Mazumder Shuvo
FLAT: Layout-Aware and Security Property-Assisted Timing Fault-Injection Attack Assessment. IEEE Trans. Very Large Scale Integr. Syst. 32(6): 1150-1163 (2024) - [j18]Md Rafid Muttaki
FTC: A Universal Framework for Fault-Injection Attack Detection and Prevention. IEEE Trans. Very Large Scale Integr. Syst. 32(7): 1311-1324 (2024) - [c75]Nusrat Farzana Dipu, Muhammad Monir Hossain, Kimia Zamiri Azar, Farimah Farahmandi, Mark M. Tehranipoor:
FormalFuzzer: Formal Verification Assisted Fuzz Testing for SoC Vulnerability Detection. ASPDAC 2024: 355-361 - [c74]Galib Ibne Haidar
GATE-SiP: Enabling Authenticated Encryption Testing in Systems-in-Package. DAC 2024: 299:1-299:6 - [c73]Nurun Nahar Mondol, Arash Vafaei, Kimia Zamiri Azar, Farimah Farahmandi, Mark M. Tehranipoor:
RL-TPG: Automated Pre-Silicon Security Verification through Reinforcement Learning-Based Test Pattern Generation. DATE 2024: 1-6 - [c72]Sajeed Mohammad
DyFORA: Dynamic Firmware Obfuscation and Remote Attestation using Hardware Signatures. ACM Great Lakes Symposium on VLSI 2024: 471-476 - [c71]Bulbul Ahmed
SeeMLess: Security Evaluation of Logic Locking using Machine Learning oriented Estimation. ACM Great Lakes Symposium on VLSI 2024: 489-494 - [c70]Avinash Ayalasomayajula, Nusrat Farzana, Debjit Pal, Farimah Farahmandi:
Prioritizing Information Flow Violations: Generation of Ranked Security Assertions for Hardware Designs. HOST 2024: 128-138 - [c69]Dipayan Saha, Katayoon Yahyaei, Sujan Kumar Saha, Mark M. Tehranipoor, Farimah Farahmandi:
Empowering Hardware Security with LLM: The Development of a Vulnerable Hardware Database. HOST 2024: 233-243 - [c68]Md Sami Ul Islam Sami, Jingbo Zhou, Sujan Kumar Saha, Fahim Rahman, Farimah Farahmandi, Mark M. Tehranipoor:
SAP: Silicon Authentication Platform for System-on-Chip Supply Chain Vulnerabilities. ISPASS 2024: 109-119 - [c67]Nashmin Alam, Tao Zhang, Farimah Farahmandi:
Towards Quantum-Resistant Security: Pre-Silicon Power Side-Channel Leakage Analysis of CRYSTALS-Kyber. ISVLSI 2024: 149-154 - [c66]Paul Calzada, Md Sami Ul Islam Sami, Jingbo Zhou, Kimia Zamiri Azar, Farimah Farahmandi, Mark M. Tehranipoor:
HI-SST: Safeguarding SiP Authenticity Through Secure Split-Test in Heterogeneous Integration. ISVLSI 2024: 379-384 - [c65]Galib Ibne Haidar, Md Sami Ul Islam Sami, Jingbo Zhou, Kimia Zamiri Azar, Mark M. Tehranipoor, Farimah Farahmandi:
SECT-HI: Enabling Secure Testing for Heterogeneous Integration to Prevent SiP Counterfeits. ITC 2024: 303-312 - [c64]Avinash Ayalasomayajula
LASP: LLM Assisted Security Property Generation for SoC Verification. MLCAD 2024: 29:1-29:7 - [c63]Bulbul Ahmed, Sujan Kumar Saha, Jingbo Zhou, Sohrab Aftabjahani, Mark M. Tehranipoor, Farimah Farahmandi:
Continuity in Security: Leveraging LLM for Translating Security Properties Across Hardware Designs. VLSI-SoC 2024: 1-6 - [c62]Sajeed Mohammad, Farimah Farahmandi:
FortBoot: Fortifying Rooted-in-Device-Specific Security Through Secure Booting. VLSI-SoC 2024: 1-4 - [c61]Sree Ranjani Rajendran, Farimah Farahmandi, Mark M. Tehranipoor:
CAD Tools Pathway in Hardware Security. VLSID 2024: 342-347 - [i23]Tao Zhang, Shang Shi, Md Habibur Rahman, Nitin Varshney, Akshay Kulkarni, Farimah Farahmandi, Mark M. Tehranipoor:
INSPECT: Investigating Supply Chain and Cyber-Physical Security of Battery Systems. IACR Cryptol. ePrint Arch. 2024: 211 (2024) - [i22]Shams Tarek, Dipayan Saha, Sujan Kumar Saha, Mark M. Tehranipoor, Farimah Farahmandi:
SoCureLLM: An LLM-driven Approach for Large-Scale System-on-Chip Security Verification and Policy Generation. IACR Cryptol. ePrint Arch. 2024: 983 (2024) - [i21]Rasheed Kibria, Farimah Farahmandi, Mark M. Tehranipoor:
A Survey on SoC Security Verification Methods at the Pre-silicon Stage. IACR Cryptol. ePrint Arch. 2024: 1280 (2024) - 2023
- [j17]M. Sazadur Rahman
ReTrustFSM: Toward RTL Hardware Obfuscation-A Hybrid FSM Approach. IEEE Access 11: 19741-19761 (2023) - [j16]Tao Zhang
FPGA-Chain: Enabling Holistic Protection of FPGA Supply Chain With Blockchain Technology. IEEE Des. Test 40(2): 127-136 (2023) - [j15]Md Sami Ul Islam Sami
Enabling Security of Heterogeneous Integration: From Supply Chain to In-Field Operations. IEEE Des. Test 40(5): 86-95 (2023) - [j14]Farimah Farahmandi
Introduction to the Special Issue on CAD for Security: Pre-silicon Security Sign-off Solutions Through Design Cycle. ACM J. Emerg. Technol. Comput. Syst. 19(1): 4:1-4:4 (2023) - [j13]Md Rafid Muttaki
HLock+: A Robust and Low-Overhead Logic Locking at the High-Level Language. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(7): 2149-2162 (2023) - [j12]Rasheed Kibria
FSMx-Ultra: Finite State Machine Extraction From Gate-Level Netlist for Security Assessment. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(11): 3613-3627 (2023) - [c60]Hasan Al Shaikh, Arash Vafaei, Mridha Md Mashahedur Rahman, Kimia Zamiri Azar, Fahim Rahman, Farimah Farahmandi, Mark M. Tehranipoor:
SHarPen: SoC Security Verification by Hardware Penetration Test. ASP-DAC 2023: 579-584 - [c59]Shang Shi, Nitin Pundir
SecHLS: Enabling Security Awareness in High-Level Synthesis. ASP-DAC 2023: 585-590 - [c58]Zahin Ibnat, M. Sazadur Rahman
ActiWate: Adaptive and Design-agnostic Active Watermarking for IP Ownership in Modern SoCs. DAC 2023: 1-6 - [c57]Rui Guo
EvoLUTe: Evaluation of Look-Up-Table-based Fine-Grained IP Redaction. DATE 2023: 1-6 - [c56]Muhammad Monir Hossain, Arash Vafaei, Kimia Zamiri Azar, Fahim Rahman, Farimah Farahmandi, Mark M. Tehranipoor:
SoCFuzzer: SoC Vulnerability Detection using Cost Function enabled Fuzz Testing. DATE 2023: 1-6 - [c55]Hadi Mardani Kamali, Kimia Zamiri Azar, Farimah Farahmandi, Mark M. Tehranipoor:
SheLL: Shrinking eFPGA Fabrics for Logic Locking. DATE 2023: 1-6 - [c54]Md Rafid Muttaki
RTLock: IP Protection using Scan-Aware Logic Locking at RTL. DATE 2023: 1-6 - [c53]Sree Ranjani Rajendran, Shams Tarek, Benjamin M. Hicks, Hadi Mardani Kamali, Farimah Farahmandi, Mark M. Tehranipoor:
HUnTer: Hardware Underneath Trigger for Exploiting SoC-level Vulnerabilities. DATE 2023: 1-6 - [c52]Zahin Ibnat, Hadi Mardani Kamali, Farimah Farahmandi:
Iterative Mitigation of Insecure Resource Sharing Produced by High-level Synthesis. DFT 2023: 1-6 - [c51]Mridha Md Mashahedur Rahman, Shams Tarek, Kimia Zamiri Azar, Farimah Farahmandi:
EnSAFe: Enabling Sustainable SoC Security Auditing using eFPGA-based Accelerators. DFT 2023: 1-6 - [c50]Hasan Al Shaikh, Mohammad Bin Monjil, Kimia Zamiri Azar, Farimah Farahmandi, Mark M. Tehranipoor, Fahim Rahman:
QuardTropy: Detecting and Quantifying Unauthorized Information Leakage in Hardware Designs using g-entropy. DFT 2023: 1-6 - [c49]Upoma Das, M. Sazadur Rahman
PSC-Watermark: Power Side Channel Based IP Watermarking Using Clock Gates. ETS 2023: 1-6 - [c48]Tao Zhang, Mark M. Tehranipoor, Farimah Farahmandi:
BitFREE: On Significant Speedup and Security Applications of FPGA Bitstream Format Reverse Engineering. ETS 2023: 1-6 - [c47]Mohammad Sazadur Rahman
Metrics-to-Methods: Decisive Reverse Engineering Metrics for Resilient Logic Locking. ACM Great Lakes Symposium on VLSI 2023: 685-690 - [c46]Muhammad Monir Hossain, Nusrat Farzana Dipu, Kimia Zamiri Azar, Fahim Rahman, Farimah Farahmandi, Mark M. Tehranipoor:
TaintFuzzer: SoC Security Verification using Taint Inference-enabled Fuzzing. ICCAD 2023: 1-9 - [c45]Shams Tarek, Hasan Al Shaikh, Sree Ranjani Rajendran, Farimah Farahmandi:
Benchmarking of SoC-Level Hardware Vulnerabilities: A Complete Walkthrough. ISVLSI 2023: 1-6 - [c44]Rasheed Kibria, Farimah Farahmandi, Mark M. Tehranipoor:
ARC-FSM-G: Automatic Security Rule Checking for Finite State Machine at the Netlist Abstraction. ITC 2023: 320-329 - [c43]Md Rafid Muttaki, Zahin Ibnat, Shang Shi, Hadi Mardani Kamali, Farimah Farahmandi:
Security of Hardware Generators: Enabling Assurance in High-Level Synthesis. MWSCAS 2023: 816-820 - [c42]Sohrab Aftabjahani, Mark M. Tehranipoor, Farimah Farahmandi, Bulbul Ahmed, Ryan Kastner, Francesco Restuccia, Andres Meza, Kaki Ryan, Nicole Fern, Jasper Van Woudenberg, Rajesh Velegalati, Cees-Bart Breunesse, Cynthia Sturton, Calvin Deutschbein:
Special Session: CAD for Hardware Security - Promising Directions for Automation of Security Assurance. VTS 2023: 1-10 - [c41]Mridha Md Mashahedur Rahman, M. Sazadur Rahman
CAPEC: A Cellular Automata Guided FSM-based IP Authentication Scheme. VTS 2023: 1-8 - [i20]Dipayan Saha, Shams Tarek, Katayoon Yahyaei, Sujan Kumar Saha, Jingbo Zhou, Mark M. Tehranipoor, Farimah Farahmandi:
LLM for SoC Security: A Paradigm Shift. CoRR abs/2310.06046 (2023) - [i19]Rasheed Kibria, Farimah Farahmandi, Mark M. Tehranipoor:
ARC-FSM-G: Automatic Security Rule Checking for Finite State Machine at the Netlist Abstraction. IACR Cryptol. ePrint Arch. 2023: 1037 (2023) - [i18]Dipayan Saha, Shams Tarek, Katayoon Yahyaei, Sujan Kumar Saha, Jingbo Zhou, Mark M. Tehranipoor, Farimah Farahmandi:
LLM for SoC Security: A Paradigm Shift. IACR Cryptol. ePrint Arch. 2023: 1561 (2023) - [i17]Amit Mazumder Shuvo, Tao Zhang, Farimah Farahmandi, Mark M. Tehranipoor:
A Comprehensive Survey on Non-Invasive Fault Injection Attacks. IACR Cryptol. ePrint Arch. 2023: 1769 (2023) - 2022
- [j11]Nitin Pundir
Analyzing Security Vulnerabilities Induced by High-level Synthesis. ACM J. Emerg. Technol. Comput. Syst. 18(3): 47:1-47:22 (2022) - [j10]Huanyu Wang
SoFI: Security Property-Driven Vulnerability Assessments of ICs Against Fault-Injection Attacks. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(3): 452-465 (2022) - [j9]Andrew Stern
ACED-IT: Assuring Confidential Electronic Design Against Insider Threats in a Zero-Trust Environment. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(10): 3202-3215 (2022) - [j8]Nidish Vashistha
eChain: A Blockchain-Enabled Ecosystem for Electronic Device Authenticity Verification. IEEE Trans. Consumer Electron. 68(1): 23-37 (2022) - [j7]Nitin Pundir
Power Side-Channel Leakage Assessment Framework at Register-Transfer Level. IEEE Trans. Very Large Scale Integr. Syst. 30(9): 1207-1218 (2022) - [c40]M. Sazadur Rahman
O'clock: lock the clock via clock-gating for SoC IP protection. DAC 2022: 775-780 - [c39]Md Rafid Muttaki
Secure by construction: addressing security vulnerabilities introduced during high-level synthesis: invited. DAC 2022: 1371-1374 - [c38]Dhwani Mehta, Nurun N. Mondol, Farimah Farahmandi, Mark M. Tehranipoor:
AIME: Watermarking AI Models by Leveraging Errors. DATE 2022: 304-309 - [c37]Nitin Pundir
Security Properties Driven Pre-Silicon Laser Fault Injection Assessment. HOST 2022: 9-12 - [c36]Kimia Zamiri Azar, Hadi Mardani Kamali, Farimah Farahmandi, Mark M. Tehranipoor:
Warm Up before Circuit De-obfuscation? An Exploration through Bounded-Model-Checkers. HOST 2022: 13-16 - [c35]Md Rafid Muttaki
FTC: A Universal Sensor for Fault Injection Attack Detection. HOST 2022: 117-120 - [c34]Amit Mazumder Shuvo, Nitin Pundir
LDTFI: Layout-aware Timing Fault-Injection Attack Assessment Against Differential Fault Analysis. ISVLSI 2022: 134-139 - [c33]Upoma Das, Md Rafid Muttaki
ADWIL: A Zero-Overhead Analog Device Watermarking Using Inherent IP Features. ITC 2022: 155-164 - [c32]Rasheed Kibria, M. Sazadur Rahman
RTL-FSMx: Fast and Accurate Finite State Machine Extraction at the RTL for Security Applications. ITC 2022: 165-174 - [c31]Rasheed Kibria, Nusrat Farzana, Farimah Farahmandi, Mark M. Tehranipoor:
FSMx: Finite State Machine Extraction from Flattened Netlist With Application to Security. VTS 2022: 1-7 - [i16]Bulbul Ahmed, Md Kawser Bepary, Nitin Pundir, Mike Borza, Oleg Raikhman, Amit Garg, Dale R. Donchin, Adam Cron, Mohamed Abdel-Moneum, Farimah Farahmandi, Fahim Rahman, Mark M. Tehranipoor:
Quantifiable Assurance: From IPs to Platforms. CoRR abs/2204.07909 (2022) - [i15]Hasan Al Shaikh, Mohammad Bin Monjil, Shigang Chen, Navid Asadizanjani, Farimah Farahmandi, Mark M. Tehranipoor, Fahim Rahman:
Digital Twin for Secure Semiconductor Lifecycle Management: Prospects and Applications. CoRR abs/2205.10962 (2022) - [i14]N. Nalla Anandakumar, M. Sazadur Rahman, Mridha Md Mashahedur Rahman, Rasheed Kibria, Upoma Das, Farimah Farahmandi, Fahim Rahman, Mark M. Tehranipoor:
Rethinking Watermark: Providing Proof of IP Ownership in Modern SoCs. IACR Cryptol. ePrint Arch. 2022: 92 (2022) - [i13]Hasan Al Shaikh, Mohammad Bin Monjil, Shigang Chen, Farimah Farahmandi, Navid Asadizanjani, Mark M. Tehranipoor, Fahim Rahman:
Digital Twin for Secure Semiconductor Lifecycle Management: Prospects and Applications. IACR Cryptol. ePrint Arch. 2022: 258 (2022) - [i12]Hadi Mardani Kamali, Kimia Zamiri Azar, Farimah Farahmandi, Mark M. Tehranipoor:
Advances in Logic Locking: Past, Present, and Prospects. IACR Cryptol. ePrint Arch. 2022: 260 (2022) - [i11]Kimia Zamiri Azar, Muhammad Monir Hossain, Arash Vafaei, Hasan Al Shaikh
Fuzz, Penetration, and AI Testing for SoC Security Verification: Challenges and Solutions. IACR Cryptol. ePrint Arch. 2022: 394 (2022) - [i10]Jungmin Park, N. Nalla Anandakumar, Dipayan Saha
PQC-SEP: Power Side-channel Evaluation Platform for Post-Quantum Cryptography Algorithms. IACR Cryptol. ePrint Arch. 2022: 527 (2022) - [i9]Sukanta Dey, Jungmin Park, Nitin Pundir, Dipayan Saha
Secure Physical Design. IACR Cryptol. ePrint Arch. 2022: 891 (2022) - [i8]Nidish Vashistha, Md Latifur Rahman, Md. Saad Ul Haque, Azim Uddin, Md Sami Ul Islam Sami
ToSHI - Towards Secure Heterogeneous Integration: Security Risks, Threat Assessment, and Assurance. IACR Cryptol. ePrint Arch. 2022: 984 (2022) - [i7]Rasheed Kibria, Farimah Farahmandi, Mark M. Tehranipoor:
FSMx-Ultra: Finite State Machine Extraction from Gate-Level Netlist for Security Assessment. IACR Cryptol. ePrint Arch. 2022: 1582 (2022) - 2021
- [j6]M. Sazadur Rahman
Security Assessment of Dynamically Obfuscated Scan Chain Against Oracle-guided Attacks. ACM Trans. Design Autom. Electr. Syst. 26(4): 29:1-29:27 (2021) - [c30]Md Rafid Muttaki
HLock: Locking IPs at the High-Level Language. DAC 2021: 79-84 - [c29]Tao Zhang, Jungmin Park, Mark M. Tehranipoor, Farimah Farahmandi:
PSC-TG: RTL Power Side-Channel Leakage Assessment with Test Pattern Generation. DAC 2021: 709-714 - [c28]Md Sami Ul Islam Sami
Invited: End-to-End Secure SoC Lifecycle Management. DAC 2021: 1295-1298 - [c27]Muhammad Monir Hossain, Farimah Farahmandi, Mark M. Tehranipoor, Fahim Rahman:
BOFT: Exploitable Buffer Overflow Detection by Information Flow Tracking. DATE 2021: 1126-1129 - [c26]Md Sami Ul Islam Sami
POCA: First Power-on Chip Authentication in Untrusted Foundry and Assembly. HOST 2021: 124-135 - [c25]Bulbul Ahmed, Fahim Rahman, Nick Hooten, Farimah Farahmandi, Mark M. Tehranipoor:
AutoMap: Automated Mapping of Security Properties Between Different Levels of Abstraction in Design Flow. ICCAD 2021: 1-9 - [c24]Sajeed Mohammad, Mridha Md Mashahedur Rahman, Farimah Farahmandi:
Required Policies and Properties of the Security Engine of an SoC. iSES 2021: 414-420 - [c23]Nitin Pundir
Secure High-Level Synthesis: Challenges and Solutions. ISQED 2021: 164-171 - [c22]Muhammad Monir Hossain, Sajeed Mohammad, Jason Vosatka, Jeffery S. Allen, Monica Allen, Farimah Farahmandi, Fahim Rahman, Mark M. Tehranipoor:
HEXON: Protecting Firmware Using Hardware-Assisted Execution-Level Obfuscation. ISVLSI 2021: 343-349 - [c21]M. Sazadur Rahman
LL-ATPG: Logic-Locking Aware Test Using Valet Keys in an Untrusted Environment. ITC 2021: 180-189 - [c20]Arash Vafaei, Nick Hooten, Mark M. Tehranipoor, Farimah Farahmandi:
SymbA: Symbolic Execution at C-level for Hardware Trojan Activation. ITC 2021: 223-232 - [c19]Sohrab Aftabjahani, Ryan Kastner
Special Session: CAD for Hardware Security - Automation is Key to Adoption of Solutions. VTS 2021: 1-10 - [c18]Nusrat Farzana, Avinash Ayalasomayajula, Fahim Rahman, Farimah Farahmandi, Mark M. Tehranipoor:
SAIF: Automated Asset Identification for Security Verification at the Register Transfer Level. VTS 2021: 1-7 - [i6]Nitin Pundir, Fahim Rahman, Farimah Farahmandi, Mark M. Tehranipoor:
What is All the FaaS About? - Remote Exploitation of FPGA-as-a-Service Platforms. IACR Cryptol. ePrint Arch. 2021: 746 (2021) - [i5]Nusrat Farzana, Farimah Farahmandi, Mark M. Tehranipoor:
SoC Security Properties and Rules. IACR Cryptol. ePrint Arch. 2021: 1014 (2021) - [i4]Fahim Rahman, Farimah Farahmandi, Mark M. Tehranipoor:
An End-to-End Bitstream Tamper Attack Against Flip-Chip FPGAs. IACR Cryptol. ePrint Arch. 2021: 1542 (2021) - [i3]Bulbul Ahmed, Md Kawser Bepary, Nitin Pundir, Mike Borza, Oleg Raikhman, Amit Garg, Dale R. Donchin, Adam Cron, Mohamed A. Abdelmoneum, Farimah Farahmandi, Fahim Rahman, Mark M. Tehranipoor:
Quantifiable Assurance: From IPs to Platforms. IACR Cryptol. ePrint Arch. 2021: 1654 (2021) - 2020
- [j5]M. Tanjidur Rahman
Defense-in-depth: A recipe for logic locking to prevail. Integr. 72: 39-57 (2020) - [j4]Adib Nahiyan, Jungmin Park, Miao Tony He, Yousef Iskander, Farimah Farahmandi, Domenic Forte
SCRIPT: A CAD Framework for Power Side-channel Vulnerability Assessment Using Information Flow Tracking and Pattern Generation. ACM Trans. Design Autom. Electr. Syst. 25(3): 26:1-26:27 (2020) - [c17]Farimah Farahmandi, Ozgur Sinanoglu
Design Obfuscation versus Test. ETS 2020: 1-10 - [c16]Andrew Stern, Dhwani Mehta, Shahin Tajik, Farimah Farahmandi, Mark M. Tehranipoor:
SPARTA: A Laser Probing Approach for Trojan Detection. ITC 2020: 1-10 - [c15]Adam Duncan, Adib Nahiyan, Fahim Rahman, Grant Skipper, Martin Swany
SeRFI: Secure Remote FPGA Initialization in an Untrusted Environment. VTS 2020: 1-6
2010 – 2019
- 2019
- [j3]Farimah Farahmandi
Automated Test Generation for Debugging Multiple Bugs in Arithmetic Circuits. IEEE Trans. Computers 68(2): 182-197 (2019) - [j2]Adib Nahiyan
Security-Aware FSM Design Flow for Identifying and Mitigating Vulnerabilities to Fault Attacks. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38(6): 1003-1016 (2019) - [c14]Adam Duncan, Fahim Rahman, Andrew Lukefahr, Farimah Farahmandi, Mark M. Tehranipoor:
FPGA Bitstream Security: A Day in the Life. ITC 2019: 1-10 - [c13]Nusrat Farzana, Fahim Rahman, Mark M. Tehranipoor, Farimah Farahmandi:
SoC Security Verification using Property Checking. ITC 2019: 1-10 - [p1]Alif Ahmed, Farimah Farahmandi, Yousef Iskander, Prabhat Mishra
Security and Trust Verification of IoT SoCs. Security and Fault Tolerance in Internet of Things 2019: 1-19 - [i2]M. Tanjidur Rahman, M. Sazadur Rahman, Huanyu Wang, Shahin Tajik, Waleed Khalil, Farimah Farahmandi, Domenic Forte, Navid Asadizanjani, Mark M. Tehranipoor:
Defense-in-Depth: A Recipe for Logic Locking to Prevail. CoRR abs/1907.08863 (2019) - [i1]M. Sazadur Rahman, Adib Nahiyan, Sarah Amir, Fahim Rahman, Farimah Farahmandi, Domenic Forte, Mark M. Tehranipoor:
Dynamically Obfuscated Scan Chain To Resist Oracle-Guided Attacks On Logic Locked Design. IACR Cryptol. ePrint Arch. 2019: 946 (2019) - 2018
- [c12]Alif Ahmed, Farimah Farahmandi, Prabhat Mishra
Directed test generation using concolic testing on RTL models. DATE 2018: 1538-1543 - [c11]Alif Ahmed, Farimah Farahmandi, Yousef Iskander, Prabhat Mishra
Scalable Hardware Trojan Activation by Interleaving Concrete Simulation and Symbolic Execution. ITC 2018: 1-10 - [c10]Jonathan Cruz, Farimah Farahmandi, Alif Ahmed, Prabhat Mishra
Hardware Trojan Detection Using ATPG and Model Checking. VLSID 2018: 91-96 - 2017
- [c9]Farimah Farahmandi, Yuanwen Huang, Prabhat Mishra
Trojan localization using symbolic algebra. ASP-DAC 2017: 591-597 - [c8]Farimah Farahmandi, Ronny Morad, Avi Ziv, Ziv Nevo, Prabhat Mishra
Cost-effective analysis of post-silicon functional coverage events. DATE 2017: 392-397 - [c7]Farimah Farahmandi, Prabhat Mishra
Automated Debugging of Arithmetic Circuits Using Incremental Gröbner Basis Reduction. ICCD 2017: 193-200 - [c6]Farimah Farahmandi, Prabhat Mishra
FSM Anomaly Detection Using Formal Analysis. ICCD 2017: 313-320 - 2016
- [c5]Farimah Farahmandi, Prabhat Mishra:
Automated test generation for Debugging arithmetic circuits. DATE 2016: 1351-1356 - [c4]Farimah Farahmandi, Prabhat Mishra, Sandip Ray:
Exploiting transaction level models for observability-aware post-silicon test generation. DATE 2016: 1477-1480 - 2015
- [j1]Farimah Farahmandi, Bijan Alizadeh:
Groebner basis based formal verification of large arithmetic circuits using Gaussian elimination and cone-based polynomial extraction. Microprocess. Microsystems 39(2): 83-96 (2015) - [c3]Xiaolong Guo, Raj Gautam Dutta, Yier Jin
Pre-silicon security verification and validation: a formal perspective. DAC 2015: 145:1-145:6 - 2014
- [c2]Farimah Farahmandi, Bijan Alizadeh, Zainalabedin Navabi:
Effective Combination of Algebraic Techniques and Decision Diagrams to Formally Verify Large Arithmetic Circuits. ISVLSI 2014: 338-343 - 2013
- [c1]Somayeh Sadeghi Kohan, Shahrzad Keshavarz, Farzaneh Zokaee, Farimah Farahmandi, Zainalabedin Navabi:
A new structure for interconnect offline testing. EWDTS 2013: 1-5
Coauthor Index
M. Sazadur Rahman
aka: Mohammad Sazadur Rahman
aka: Mohammad Sazadur Rahman
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