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Francesco Restuccia 0002
Person information
- affiliation: University of California at San Diego, San Diego, CA, USA
Other persons with the same name
- Francesco Restuccia 0001
— Northeastern University, Boston, MA, USA (and 1 more)
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2020 – today
- 2024
- [j11]Luca Valente, Francesco Restuccia, Davide Rossi, Ryan Kastner, Luca Benini:
TOP: Towards Open & Predictable Heterogeneous SoCs. IEEE Trans. Computers 73(12): 2678-2692 (2024) - [c11]Thomas Benz, Alessandro Ottaviano, Robert Balas, Angelo Garofalo, Francesco Restuccia, Alessandro Biondi, Luca Benini:
AXI-REALM: A Lightweight and Modular Interconnect Extension for Traffic Regulation and Monitoring of Heterogeneous Real-Time SoCs. DATE 2024: 1-6 - [i5]Luca Valente, Francesco Restuccia, Davide Rossi, Ryan Kastner, Luca Benini:
TOP: Towards Open & Predictable Heterogeneous SoCs. CoRR abs/2401.15639 (2024) - [i4]G. Abarajithan, Zhenghua Ma, Zepeng Li, Shrideep Koparkar, Ravidu Munasinghe, Francesco Restuccia, Ryan Kastner:
CGRA4ML: A Framework to Implement Modern Neural Networks for Scientific Edge Computing. CoRR abs/2408.15561 (2024) - 2023
- [j10]Andres Meza
Security Verification of the OpenTitan Hardware Root of Trust. IEEE Secur. Priv. 21(3): 27-36 (2023) - [j9]Calvin Deutschbein
Isadora: automated information-flow property generation for hardware security verification. J. Cryptogr. Eng. 13(4): 391-407 (2023) - [j8]Francesco Restuccia
Bounding Memory Access Times in Multi-Accelerator Architectures on FPGA SoCs. IEEE Trans. Computers 72(1): 154-167 (2023) - [j7]Francesco Restuccia
A Framework for Design, Verification, and Management of SoC Access Control Systems. IEEE Trans. Computers 72(2): 386-400 (2023) - [c10]Sohrab Aftabjahani, Mark M. Tehranipoor, Farimah Farahmandi, Bulbul Ahmed, Ryan Kastner, Francesco Restuccia, Andres Meza, Kaki Ryan, Nicole Fern, Jasper Van Woudenberg, Rajesh Velegalati, Cees-Bart Breunesse, Cynthia Sturton, Calvin Deutschbein:
Special Session: CAD for Hardware Security - Promising Directions for Automation of Security Assurance. VTS 2023: 1-10 - [i3]Thomas Benz, Alessandro Ottaviano, Robert Balas, Angelo Garofalo, Francesco Restuccia, Alessandro Biondi
AXI-REALM: A Lightweight and Modular Interconnect Extension for Traffic Regulation and Monitoring of Heterogeneous Real-Time SoCs. CoRR abs/2311.09662 (2023) - 2022
- [j6]Michael Barrow
A Remote Control System for Emergency Ventilators During SARS-CoV-2. IEEE Embed. Syst. Lett. 14(1): 43-46 (2022) - [j5]Calvin Deutschbein
Toward Hardware Security Property Generation at Scale. IEEE Secur. Priv. 20(3): 43-51 (2022) - [j4]Francesco Restuccia
ARTe: Providing real-time multitasking to Arduino. J. Syst. Softw. 186: 111185 (2022) - [j3]Francesco Restuccia
Cut and Forward: Safe and Secure Communication for FPGA System on Chips. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(11): 4052-4063 (2022) - [c9]Ryan Kastner, Francesco Restuccia, Andres Meza, Sayak Ray, Jason M. Fung, Cynthia Sturton:
Automating hardware security property generation: invited. DAC 2022: 1384-1387 - [c8]Gerlando Sciangula, Francesco Restuccia, Alessandro Biondi
Hardware Acceleration of Deep Neural Networks for Autonomous Driving on FPGA-based SoC. DSD 2022: 406-414 - [c7]Gabriele Serra
PAC-PL: Enabling Control-Flow Integrity with Pointer Authentication in FPGA SoC Platforms. RTAS 2022: 241-253 - 2021
- [c6]Calvin Deutschbein
Isadora: Automated Information Flow Property Generation for Hardware Designs. ASHES@CCS 2021: 5-15 - [c5]Francesco Restuccia, Andres Meza, Ryan Kastner:
Aker: A Design and Verification Framework for Safe and Secure SoC Access Control. ICCAD 2021: 1-9 - [c4]Francesco Restuccia, Alessandro Biondi
Time-Predictable Acceleration of Deep Neural Networks on FPGA SoC Platforms. RTSS 2021: 441-454 - [i2]Calvin Deutschbein, Andres Meza, Francesco Restuccia, Ryan Kastner, Cynthia Sturton:
A Methodology For Creating Information Flow Specifications of Hardware Designs. CoRR abs/2106.07449 (2021) - [i1]Francesco Restuccia, Andres Meza, Ryan Kastner:
AKER: A Design and Verification Framework for Safe andSecure SoC Access Control. CoRR abs/2106.13263 (2021) - 2020
- [j2]Francesco Restuccia, Marco Pagani, Alessandro Biondi, Mauro Marinoni, Giorgio C. Buttazzo:
Modeling and Analysis of Bus Contention for Hardware Accelerators in FPGA SoCs (Artifact). Dagstuhl Artifacts Ser. 6(1): 04:1-04:3 (2020) - [c3]Francesco Restuccia, Alessandro Biondi
AXI HyperConnect: A Predictable, Hypervisor-level Interconnect for Hardware Accelerators in FPGA SoC. DAC 2020: 1-6 - [c2]Francesco Restuccia, Marco Pagani, Alessandro Biondi
Modeling and Analysis of Bus Contention for Hardware Accelerators in FPGA SoCs. ECRTS 2020: 12:1-12:23 - [c1]Francesco Restuccia, Alessandro Biondi
Safely Preventing Unbounded Delays During Bus Transactions in FPGA-based SoC. FCCM 2020: 129-137
2010 – 2019
- 2019
- [j1]Francesco Restuccia, Marco Pagani, Alessandro Biondi
Is Your Bus Arbiter Really Fair? Restoring Fairness in AXI Interconnects for FPGA SoCs. ACM Trans. Embed. Comput. Syst. 18(5s): 51:1-51:22 (2019)
Coauthor Index
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last updated on 2024-12-13 19:11 CET by the dblp team
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