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Hadi Mardani Kamali
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2020 – today
- 2024
- [j14]Md Sami Ul Islam Sami
, Tao Zhang
Advancing Trustworthiness in System-in-Package: A Novel Root-of-Trust Hardware Security Module for Heterogeneous Integration. IEEE Access 12: 48081-48107 (2024) - [j13]Kimia Zamiri Azar, Hadi Mardani Kamali
Improving Bounded Model Checkers Scalability for Circuit De-Obfuscation: An Exploration. IEEE Trans. Inf. Forensics Secur. 19: 2771-2785 (2024) - [j12]Sree Ranjani Rajendran
Exploring the Abyss? Unveiling Systems-on-Chip Hardware Vulnerabilities Beneath Software. IEEE Trans. Inf. Forensics Secur. 19: 3914-3926 (2024) - [j11]Tao Zhang
SiPGuard: Run-Time System-in-Package Security Monitoring via Power Noise Variation. IEEE Trans. Very Large Scale Integr. Syst. 32(2): 305-318 (2024) - [c32]Galib Ibne Haidar
GATE-SiP: Enabling Authenticated Encryption Testing in Systems-in-Package. DAC 2024: 299:1-299:6 - [c31]Mohammad Akyash
Evolutionary Large Language Models for Hardware Security: A Comparative Survey. ACM Great Lakes Symposium on VLSI 2024: 496-501 - [c30]Mohammad Akyash, Hadi Mardani Kamali:
Self-HWDebug: Automation of LLM Self-Instructing for Hardware Security Verification. ISVLSI 2024: 391-396 - [i16]Mohammad A. Makhzan, Hadi Mardani Kamali:
Evolutionary Large Language Models for Hardware Security: A Comparative Survey. CoRR abs/2404.16651 (2024) - [i15]Mohammad Akyash, Hadi Mardani Kamali:
Self-HWDebug: Automation of LLM Self-Instructing for Hardware Security Verification. CoRR abs/2405.12347 (2024) - 2023
- [j10]M. Sazadur Rahman
ReTrustFSM: Toward RTL Hardware Obfuscation-A Hybrid FSM Approach. IEEE Access 11: 19741-19761 (2023) - [j9]Md Sami Ul Islam Sami
Enabling Security of Heterogeneous Integration: From Supply Chain to In-Field Operations. IEEE Des. Test 40(5): 86-95 (2023) - [j8]Md Rafid Muttaki
HLock+: A Robust and Low-Overhead Logic Locking at the High-Level Language. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(7): 2149-2162 (2023) - [c29]Shang Shi, Nitin Pundir
SecHLS: Enabling Security Awareness in High-Level Synthesis. ASP-DAC 2023: 585-590 - [c28]Zahin Ibnat, M. Sazadur Rahman
ActiWate: Adaptive and Design-agnostic Active Watermarking for IP Ownership in Modern SoCs. DAC 2023: 1-6 - [c27]Rui Guo
EvoLUTe: Evaluation of Look-Up-Table-based Fine-Grained IP Redaction. DATE 2023: 1-6 - [c26]Hadi Mardani Kamali, Kimia Zamiri Azar, Farimah Farahmandi, Mark M. Tehranipoor:
SheLL: Shrinking eFPGA Fabrics for Logic Locking. DATE 2023: 1-6 - [c25]Md Rafid Muttaki
RTLock: IP Protection using Scan-Aware Logic Locking at RTL. DATE 2023: 1-6 - [c24]Sree Ranjani Rajendran, Shams Tarek, Benjamin M. Hicks, Hadi Mardani Kamali, Farimah Farahmandi, Mark M. Tehranipoor:
HUnTer: Hardware Underneath Trigger for Exploiting SoC-level Vulnerabilities. DATE 2023: 1-6 - [c23]Zahin Ibnat, Hadi Mardani Kamali, Farimah Farahmandi:
Iterative Mitigation of Insecure Resource Sharing Produced by High-level Synthesis. DFT 2023: 1-6 - [c22]Mohammad Sazadur Rahman
Metrics-to-Methods: Decisive Reverse Engineering Metrics for Resilient Logic Locking. ACM Great Lakes Symposium on VLSI 2023: 685-690 - [c21]Md Rafid Muttaki, Zahin Ibnat, Shang Shi, Hadi Mardani Kamali, Farimah Farahmandi:
Security of Hardware Generators: Enabling Assurance in High-Level Synthesis. MWSCAS 2023: 816-820 - 2022
- [c20]M. Sazadur Rahman
O'clock: lock the clock via clock-gating for SoC IP protection. DAC 2022: 775-780 - [c19]Kimia Zamiri Azar, Hadi Mardani Kamali, Farimah Farahmandi, Mark M. Tehranipoor:
Warm Up before Circuit De-obfuscation? An Exploration through Bounded-Model-Checkers. HOST 2022: 13-16 - [i14]Hadi Mardani Kamali, Kimia Zamiri Azar, Farimah Farahmandi, Mark M. Tehranipoor:
Advances in Logic Locking: Past, Present, and Prospects. IACR Cryptol. ePrint Arch. 2022: 260 (2022) - [i13]Hadi Mardani Kamali:
Secure and Robust Key-Trapped Design-for-Security Architecture for Protecting Obfuscated Logic. IACR Cryptol. ePrint Arch. 2022: 801 (2022) - 2021
- [j7]Kimia Zamiri Azar, Hadi Mardani Kamali
From Cryptography to Logic Locking: A Survey on the Architecture Evolution of Secure Scan Chains. IEEE Access 9: 73133-73151 (2021) - [j6]Zhiqian Chen, Lei Zhang, Gaurav Kolhe, Hadi Mardani Kamali, Setareh Rafatirad, Sai Manoj Pudukotai Dinakarrao, Houman Homayoun, Chang-Tien Lu
Deep Graph Learning for Circuit Deobfuscation. Frontiers Big Data 4: 608286 (2021) - [j5]Kimia Zamiri Azar, Hadi Mardani Kamali
Data Flow Obfuscation: A New Paradigm for Obfuscating Circuits. IEEE Trans. Very Large Scale Integr. Syst. 29(4): 643-656 (2021) - [c18]Shervin Roshanisefat, Hadi Mardani Kamali, Houman Homayoun, Avesta Sasan:
RANE: An Open-Source Formal De-obfuscation Attack for Reverse Engineering of Logic Encrypted Circuits. ACM Great Lakes Symposium on VLSI 2021: 221-228 - [c17]Hadi Mardani Kamali, Kimia Zamiri Azar, Houman Homayoun, Avesta Sasan:
ChaoLock: Yet Another SAT-hard Logic Locking using Chaos Computing. ISQED 2021: 387-394 - 2020
- [j4]Shervin Roshanisefat
SAT-Hard Cyclic Logic Obfuscation for Protecting the IP in the Manufacturing Supply Chain. IEEE Trans. Very Large Scale Integr. Syst. 28(4): 954-967 (2020) - [c16]Hadi Mardani Kamali, Kimia Zamiri Azar, Houman Homayoun, Avesta Sasan:
On Designing Secure and Robust Scan Chain for Protecting Obfuscated Logic. ACM Great Lakes Symposium on VLSI 2020: 217-222 - [c15]Hadi Mardani Kamali, Kimia Zamiri Azar, Houman Homayoun, Avesta Sasan:
InterLock: An Intercorrelated Logic and Routing Locking. ICCAD 2020: 78:1-78:9 - [c14]Kimia Zamiri Azar, Hadi Mardani Kamali, Houman Homayoun, Avesta Sasan:
NNgSAT: Neural Network guided SAT Attack on Logic Locked Complex Structures. ICCAD 2020: 79:1-79:9 - [c13]Hadi Mardani Kamali, Kimia Zamiri Azar, Houman Homayoun, Avesta Sasan:
SCRAMBLE: The State, Connectivity and Routing Augmentation Model for Building Logic Encryption. ISVLSI 2020: 153-159 - [c12]Shervin Roshanisefat, Hadi Mardani Kamali, Kimia Zamiri Azar, Sai Manoj Pudukotai Dinakarrao
DFSSD: Deep Faults and Shallow State Duality, A Provably Strong Obfuscation Solution for Circuits with Restricted Access to Scan Chain. VTS 2020: 1-6 - [i12]Shervin Roshanisefat, Hadi Mardani Kamali, Houman Homayoun, Avesta Sasan:
SAT-hard Cyclic Logic Obfuscation for Protecting the IP in the Manufacturing Supply Chain. CoRR abs/2001.08999 (2020) - [i11]Shervin Roshanisefat, Hadi Mardani Kamali, Kimia Zamiri Azar, Sai Manoj Pudukotai Dinakarrao, Naghmeh Karimi, Houman Homayoun, Avesta Sasan:
DFSSD: Deep Faults and Shallow State Duality, A Provably Strong Obfuscation Solution for Circuits with Restricted Access to Scan Chain. CoRR abs/2002.07857 (2020) - [i10]Hadi Mardani Kamali, Kimia Zamiri Azar, Shervin Roshanisefat, Ashkan Vakil, Avesta Sasan:
ExTru: A Lightweight, Fast, and Secure Expirable Trust for the Internet of Things. CoRR abs/2004.06235 (2020) - [i9]Hadi Mardani Kamali, Kimia Zamiri Azar, Houman Homayoun, Avesta Sasan:
On Designing Secure and Robust Scan Chain for Protecting Obfuscated Logic. CoRR abs/2005.04262 (2020) - [i8]Hadi Mardani Kamali, Kimia Zamiri Azar, Houman Homayoun, Avesta Sasan:
SCRAMBLE: The State, Connectivity and Routing Augmentation Model for Building Logic Encryption. CoRR abs/2005.11789 (2020) - [i7]Hadi Mardani Kamali, Kimia Zamiri Azar, Houman Homayoun, Avesta Sasan:
InterLock: An Intercorrelated Logic and Routing Locking. CoRR abs/2009.02206 (2020) - [i6]Kimia Zamiri Azar, Hadi Mardani Kamali, Houman Homayoun, Avesta Sasan:
NNgSAT: Neural Network guided SAT Attack on Logic Locked Complex Structures. CoRR abs/2009.02208 (2020)
2010 – 2019
- 2019
- [j3]Kimia Zamiri Azar, Hadi Mardani Kamali, Houman Homayoun, Avesta Sasan:
SMT Attack: Next Generation Attack on Obfuscated Circuits with Capabilities and Performance Beyond the SAT Attacks. IACR Trans. Cryptogr. Hardw. Embed. Syst. 2019(1): 97-122 (2019) - [c11]Hadi Mardani Kamali, Kimia Zamiri Azar, Houman Homayoun, Avesta Sasan:
Full-Lock: Hard Distributions of SAT instances for Obfuscating Circuits using Fully Configurable Logic and Routing Blocks. DAC 2019: 89 - [c10]Kimia Zamiri Azar, Hadi Mardani Kamali, Houman Homayoun, Avesta Sasan:
Threats on Logic Locking: A Decade Later. ACM Great Lakes Symposium on VLSI 2019: 471-476 - [c9]Gaurav Kolhe, Hadi Mardani Kamali, Miklesh Naicker, Tyler David Sheaves
Security and Complexity Analysis of LUT-based Obfuscation: From Blueprint to Reality. ICCAD 2019: 1-8 - [c8]Hossein Farrokhbakht, Hadi Mardani Kamali, Natalie D. Enright Jerger
Muffin: Minimally-Buffered Zero-Delay Power-Gating Technique in On-Chip Routers. ISLPED 2019: 1-6 - [c7]Kimia Zamiri Azar, Farnoud Farahmand, Hadi Mardani Kamali, Shervin Roshanisefat, Houman Homayoun, William Diehl, Kris Gaj, Avesta Sasan:
COMA: Communication and Obfuscation Management Architecture. RAID 2019: 181-195 - [i5]Kimia Zamiri Azar, Hadi Mardani Kamali, Houman Homayoun, Avesta Sasan:
Threats on Logic Locking: A Decade Later. CoRR abs/1905.05896 (2019) - [i4]Kimia Zamiri Azar, Farnoud Farahmand, Hadi Mardani Kamali, Shervin Roshanisefat, Houman Homayoun, William Diehl, Kris Gaj, Avesta Sasan:
COMA: Communication and Obfuscation Management Architecture. CoRR abs/1909.00493 (2019) - 2018
- [j2]Hadi Mardani Kamali
DuCNoC: A High-Throughput FPGA-Based NoC Simulator Using Dual-Clock Lightweight Router Micro-Architecture. IEEE Trans. Computers 67(2): 208-221 (2018) - [c6]Shervin Roshanisefat, Hadi Mardani Kamali, Avesta Sasan:
SRCLock: SAT-Resistant Cyclic Logic Locking for Protecting the Hardware. ACM Great Lakes Symposium on VLSI 2018: 153-158 - [c5]Hadi Mardani Kamali, Avesta Sasan:
MUCH-SWIFT: A High-Throughput Multi-Core HW/SW Co-design K-means Clustering Architecture. ACM Great Lakes Symposium on VLSI 2018: 459-462 - [c4]Hossein Farrokhbakht, Hadi Mardani Kamali, Natalie D. Enright Jerger
SPONGE: A Scalable Pivot-based On/Off Gating Engine for Reducing Static Power in NoC Routers. ISLPED 2018: 17:1-17:6 - [c3]Hadi Mardani Kamali, Kimia Zamiri Azar, Kris Gaj, Houman Homayoun, Avesta Sasan:
LUT-Lock: A Novel LUT-Based Logic Obfuscation for FPGA-Bitstream and ASIC-Hardware Protection. ISVLSI 2018: 405-410 - [i3]Shervin Roshanisefat, Hadi Mardani Kamali, Avesta Sasan:
SRCLock: SAT-Resistant Cyclic Logic Locking for Protecting the Hardware. CoRR abs/1804.09162 (2018) - [i2]Hadi Mardani Kamali, Kimia Zamiri Azar, Kris Gaj, Houman Homayoun, Avesta Sasan:
LUT-Lock: A Novel LUT-based Logic Obfuscation for FPGA-Bitstream and ASIC-Hardware Protection. CoRR abs/1804.11275 (2018) - [i1]Hadi Mardani Kamali:
Using Multi-Core HW/SW Co-design Architecture for Accelerating K-means Clustering Algorithm. CoRR abs/1807.09250 (2018) - 2017
- [c2]Hossein Farrokhbakht, Hadi Mardani Kamali, Shaahin Hessabi:
SMART: A Scalable Mapping And Routing Technique for Power-Gating in NoC Routers. NOCS 2017: 15:1-15:8 - 2016
- [j1]Hadi Mardani Kamali, Shaahin Hessabi
A Fault Tolerant Parallelism Approach for Implementing High-Throughput Pipelined Advanced Encryption Standard. J. Circuits Syst. Comput. 25(9): 1650113:1-1650113:14 (2016) - [c1]Hadi Mardani Kamali, Shaahin Hessabi:
AdapNoC: A fast and flexible FPGA-based NoC simulator. FPL 2016: 1-8
Coauthor Index
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