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Journal Articles
- 2024
- [j46]Muayad J. Aljafar, Florence Azaïs, Marie-Lise Flottes, Samuel Pagliarini:
Utilizing layout effects for analog logic locking. J. Cryptogr. Eng. 14(2): 311-324 (2024) - 2023
- [j45]Hassan El Badawi, Florence Azaïs, Serge Bernard, Mariane Comte, Vincent Kerzerho, Francois Lefevre:
On the Use of the Indirect Test Strategy for Lifetime Performance Monitoring of RF Circuits. J. Electron. Test. 39(2): 155-170 (2023) - 2021
- [j44]Hassan El Badawi, Florence Azaïs, Serge Bernard, Mariane Comte, Vincent Kerzerho, Francois Lefevre:
Evaluation of a Two-Tier Adaptive Indirect Test Flow for a Front-End RF Circuit. J. Electron. Test. 37(2): 225-242 (2021) - [j43]T. Vayssade
, Florence Azaïs, Laurent Latorre, François Lefèvre
Low-Cost EVM Measurement of ZigBee Transmitters From 1-bit Undersampled Acquisition. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 40(11): 2400-2410 (2021) - 2020
- [j42]Hassan El Badawi, Florence Azaïs, Serge Bernard, Mariane Comte, Vincent Kerzerho, Francois Lefevre:
Investigations on the Use of Ensemble Methods for Specification-Oriented Indirect Test of RF Circuits. J. Electron. Test. 36(2): 189-203 (2020) - 2019
- [j41]Amit Karel, Florence Azaïs, Mariane Comte, Jean-Marc Gallière, Michel Renovell:
Analytical Models for the Evaluation of Resistive Short Defect Detectability in Presence of Process Variations: Application to 28nm Bulk and FDSOI Technologies. J. Electron. Test. 35(1): 59-75 (2019) - 2018
- [j40]Stephane David-Grignot, Achraf Lamlih, Mohamed Moez Belhaj, Vincent Kerzerho, Florence Azaïs, Fabien Soulier
On-chip Generation of Sine-wave Summing Digital Signals: an Analytic Study Considering Implementation Constraints. J. Electron. Test. 34(3): 281-290 (2018) - 2017
- [j39]Amit Karel
Resistive Bridging Defect Detection in Bulk, FDSOI and FinFET Technologies. J. Electron. Test. 33(4): 515-527 (2017) - 2016
- [j38]Florence Azaïs, Stephane David-Grignot, Laurent Latorre, Francois Lefevre:
SSB Phase Noise Evaluation of Analog/IF Signals on Standard Digital ATE. J. Electron. Test. 32(1): 69-82 (2016) - [j37]Florence Azaïs, Stephane David-Grignot, Laurent Latorre, Francois Lefevre:
Digital Embedded Test Instrument for On-Chip Phase Noise Testing of Analog/RF Integrated Circuits. J. Circuits Syst. Comput. 25(3): 1640014:1-1640014:18 (2016) - 2015
- [j36]Stephane David-Grignot, Florence Azaïs, Laurent Latorre, Francois Lefevre:
Phase Noise Testing of Analog/IF Signals Using Digital ATE: A New Post-Processing Algorithm for Extended Measurement Range. J. Electron. Test. 31(5-6): 443-459 (2015) - [j35]Syhem Larguech, Florence Azaïs, Serge Bernard
Efficiency evaluation of analog/RF alternate test: Comparative study of indirect measurement selection strategies. Microelectron. J. 46(11): 1091-1102 (2015) - 2014
- [j34]Ahmed Amine Rekik, Florence Azaïs, Frédérick Mailly
Study of Low-Cost Electrical Test Strategies for Post-Silicon Yield Improvement of MEMS Convective Accelerometers. J. Electron. Test. 30(1): 87-100 (2014) - [j33]Jean-Marc Gallière, Florence Azaïs, Mariane Comte, Michel Renovell:
Testing for gate oxide short defects using the detectability interval paradigm. it Inf. Technol. 56(4): 173-181 (2014) - [j32]Haithem Ayari, Florence Azaïs, Serge Bernard
Enhancing confidence in indirect analog/RF testing against the lack of correlation between regular parameters and indirect measurements. Microelectron. J. 45(3): 336-344 (2014) - 2013
- [j31]Vincent Kerzerho, Serge Bernard
A novel implementation of the histogram-based technique for measurement of INL of LUT-based correction of ADC. Microelectron. J. 44(9): 840-843 (2013) - 2011
- [j30]Nicolas Pous, Florence Azaïs, Laurent Latorre, Jochen Rivoir:
A Level-Crossing Approach for the Analysis of RF Modulated Signals Using Only Digital Test Resources. J. Electron. Test. 27(3): 289-303 (2011) - [j29]Vincent Kerzerho, Mariane Comte, Florence Azaïs, Philippe Cauvet, Serge Bernard
Digital Test Method for Embedded Converters with Unknown-Phase Harmonics. J. Electron. Test. 27(3): 335-350 (2011) - [j28]Ahmed Amine Rekik, Florence Azaïs, Norbert Dumas, Frédérick Mailly
A Behavioral Model of MEMS Convective Accelerometers for the Evaluation of Design and Calibration Strategies at System Level. J. Electron. Test. 27(3): 411-423 (2011) - 2010
- [j27]Norbert Dumas, Florence Azaïs, Frédérick Mailly
Study of an Electrical Setup for Capacitive MEMS Accelerometers Test and Calibration. J. Electron. Test. 26(1): 111-125 (2010) - 2009
- [j26]Jean-Robert Manouvrier, Pascal Fonteneau, Charles-Alexandre Legrand, Pascal Nouet, Florence Azaïs:
Characterization of the transient behavior of gated/STI diodes and their associated BJT in the CDM time domain. Microelectron. Reliab. 49(12): 1424-1432 (2009) - 2008
- [j25]Vincent Kerzerho, Philippe Cauvet, Serge Bernard
ADC Production Test Technique Using Low-Resolution Arbitrary Waveform Generator. VLSI Design 2008: 482159:1-482159:8 (2008) - 2007
- [j24]Vincent Kerzerho, Philippe Cauvet, Serge Bernard
Fully digital test solution for a set of ADCs and DACs embedded in a SIP or SOC. IET Comput. Digit. Tech. 1(3): 146-153 (2007) - 2006
- [j23]Vincent Kerzerho, Philippe Cauvet, Serge Bernard
A Novel DFT Technique for Testing Complete Sets of ADCs and DACs in Complex SiPs. IEEE Des. Test Comput. 23(3): 234-243 (2006) - [j22]Norbert Dumas, Florence Azaïs, Laurent Latorre, Pascal Nouet:
Electro-thermal Stimuli for MEMS Testing in FSBM Technology. J. Electron. Test. 22(2): 189-198 (2006) - [j21]Christophe Entringer, Philippe Flatresse, Philippe Galy, Florence Azaïs, Pascal Nouet
Electro-thermal short pulsed simulation for SOI technology. Microelectron. Reliab. 46(9-11): 1482-1485 (2006) - 2005
- [j20]Florence Azaïs, Marcelo Lubaszewski, Pascal Nouet, Michel Renovell:
A Strategy for Optimal Test Point Insertion in Analog Cascaded Filters. J. Electron. Test. 21(1): 9-16 (2005) - [j19]Tiago R. Balen, Antonio Q. Andrade, Florence Azaïs, Marcelo Lubaszewski, Michel Renovell:
Applying the Oscillation Test Strategy to FPAA's Configurable Analog Blocks. J. Electron. Test. 21(2): 135-146 (2005) - [j18]Florence Azaïs, Serge Bernard
Efficiency of Optimized Dynamic Test Flows for ADCs: Sensitivity to Specifications. J. Electron. Test. 21(3): 291-298 (2005) - [j17]Jean Marc Gallière, Michel Renovell, Florence Azaïs, Yves Bertrand:
Delay Testing Viability of Gate Oxide Short Defects. J. Comput. Sci. Technol. 20(2): 195-200 (2005) - [j16]Antonio Andrade Jr., Gustavo Vieira, Tiago R. Balen, Marcelo Lubaszewski, Florence Azaïs, Michel Renovell:
Built-in self-test of global interconnects of field programmable analog arrays. Microelectron. J. 36(12): 1112-1123 (2005) - [j15]Florence Azaïs, B. Caillard, S. Dournelle, P. Salomé, Pascal Nouet:
A new multi-finger SCR-based structure for efficient on-chip ESD protection. Microelectron. Reliab. 45(2): 233-243 (2005) - 2004
- [j14]Serge Bernard
Efficiency of Spectral-Based ADC Test Flows to Detect Static Errors. J. Electron. Test. 20(3): 257-267 (2004) - [j13]Florence Azaïs, Serge Bernard
Correlation Between Static and Dynamic Parameters of A-to-D Converters: In the View of a Unique Test Procedure. J. Electron. Test. 20(4): 375-387 (2004) - [j12]D. Martin, Romain Desplats, Gérald Haller, Pascal Nouet, Florence Azaïs:
Automated Diagnosis and Probing Flow for Fast Fault Localization in IC. Microelectron. Reliab. 44(9-11): 1553-1558 (2004) - 2003
- [j11]Florence Azaïs, Yves Bertrand, Michel Renovell, André Ivanov, Sassan Tabatabaei:
An All-Digital DFT Scheme for Testing Catastrophic Faults in PLLs. IEEE Des. Test Comput. 20(1): 60-67 (2003) - [j10]Uros Kac, Franc Novak, Florence Azaïs, Pascal Nouet
Extending IEEE Std. 1149.4 Analog Boundary Modules to Enhance Mixed-Signal Test. IEEE Des. Test Comput. 20(2): 32-39 (2003) - [j9]Michel Renovell, Jean Marc Gallière, Florence Azaïs, Yves Bertrand:
Modeling the Random Parameters Effects in a Non-Split Model of Gate Oxide Short. J. Electron. Test. 19(4): 377-386 (2003) - [j8]Serge Bernard
On-Chip Generation of Ramp and Triangle-Wave Stimuli for ADC BIST. J. Electron. Test. 19(4): 469-479 (2003) - [j7]Florence Azaïs, Serge Bernard
A-to-D converters static error detection from dynamic parameter measurement. Microelectron. J. 34(10): 945-953 (2003) - 2002
- [j6]Michel Renovell, Florence Azaïs, Yves Bertrand:
Improving Defect Detection in Static-Voltage Testing. IEEE Des. Test Comput. 19(6): 83-89 (2002) - 2001
- [j5]Florence Azaïs, Serge Bernard
A Low-Cost BIST Architecture for Linear Histogram Testing of ADCs. J. Electron. Test. 17(2): 139-147 (2001) - [j4]Florence Azaïs, Serge Bernard
Optimizing Sinusoidal Histogram Test for Low Cost ADC BIST. J. Electron. Test. 17(3-4): 255-266 (2001) - [j3]André Ivanov, Sumbal Rafiq, Michel Renovell, Florence Azaïs, Yves Bertrand:
On the detectability of CMOS floating gate transistor faults. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 20(1): 116-128 (2001) - 2000
- [j2]Michel Renovell, Florence Azaïs, J.-C. Bodin, Yves Bertrand:
Combining Functional and Structural Approaches for Switched-Current Circuit Testing. J. Electron. Test. 16(3): 259-267 (2000) - 1999
- [j1]Michel Renovell, Florence Azaïs, Yves Bertrand:
Detection of Defects Using Fault Model Oriented Test Sequences. J. Electron. Test. 14(1-2): 13-22 (1999)
Conference and Workshop Papers
- 2024
- [c90]K. Tahraoui, R. Burelle, T. Vayssade, F. Lefevre, Laurent Latorre, Florence Azaïs:
Digital Generation of RF Phase-Modulated Test Stimuli: Application to BPSK Modulation Scheme. DFT 2024: 1-6 - [c89]Stéphane Pitou, Florence Azaïs, Serge Bernard, Tristan Rouyer, Fabien Soulier, Vincent Kerzerho:
Low-Resource Fully-Digital BPSK Demodulation Technique for Intra-Body Wireless Sensor Networks. I2MTC 2024: 1-6 - [c88]Sophie Dupuis, Nassim Riadi
Logic Locking: Exploration of a new key-gate based on tristate logic. LATS 2024: 1-6 - [c87]K. Tahraoui, T. Vayssade, François Lefèvre, Laurent Latorre, Florence Azaïs:
Digital generation of single tone FM/PM test stimuli: a theoretical analysis. LATS 2024: 1-6 - 2023
- [c86]Thibault Vayssade, Florence Azaïs, Laurent Latorre, François Lefèvre:
Low-cost digital solution for production test of ZigBee transmitters Special Session "AMS-RF testing". LATS 2023: 1-2 - 2022
- [c85]Muayad J. Aljafar, Florence Azaïs, Marie-Lise Flottes, Samuel Pagliarini:
Leveraging Layout-based Effects for Locking Analog ICs. ASHES@CCS 2022: 5-13 - 2021
- [c84]Thibault Vayssade, Florence Azaïs, Laurent Latorre, François Lefèvre:
Digital test of ZigBee transmitters: Validation in industrial test environment. DATE 2021: 396-401 - [c83]Thibault Vayssade, Mouhamad Chehaitly, Florence Azaïs, Laurent Latorre, François Lefèvre:
Exploration of a digital-based solution for the generation of 2.4GHz OQPSK test stimuli. ETS 2021: 1-6 - [c82]Hassan El Badawi, Florence Azaïs, Serge Bernard, Mariane Comte, Vincent Kerzèrho, François Lefèvre:
Exploring on-line RF performance monitoring based on the indirect test strategy. LATS 2021: 1-7 - 2020
- [c81]T. Vayssade, Florence Azaïs, Laurent Latorre, François Lefevre:
EVM measurement of RF ZigBee transceivers using standard digital ATE. DFT 2020: 1-6 - [c80]Florence Azaïs, Serge Bernard, Mariane Comte, Bastien Deveautour, Sophie Dupuis, Hassan El Badawi, Marie-Lise Flottes, Patrick Girard, Vincent Kerzèrho, Laurent Latorre, François Lefèvre, Bruno Rouzeyre, Emanuele Valea
Development and Application of Embedded Test Instruments to Digital, Analog/RFs and Secure ICs. IOLTS 2020: 1-4 - [c79]Hassan El Badawi, Florence Azaïs, Serge Bernard, Mariane Comte, Vincent Kerzèrho, Francois Lefevre, I. Gorenflot:
Implementing indirect test of RF circuits without compromising test quality: a practical case study. LATS 2020: 1-6 - 2019
- [c78]T. Vayssade, Florence Azaïs, Laurent Latorre, Francois Lefevre:
Power Measurement and Spectral Test of ZigBee Transmitters from 1-bit Under-sampled Acquisition. ETS 2019: 1-6 - [c77]Hassan El Badawi, Florence Azaïs, Serge Bernard
Use of ensemble methods for indirect test of RF circuits: can it bring benefits? LATS 2019: 1-6 - [c76]Hassan El Badawi, Mariane Comte, Florence Azaïs, Vincent Kerzèrho, Serge Bernard, François Lefevre:
Which metrics to use for RF indirect test strategy? SMACD 2019: 73-76 - 2018
- [c75]T. Vayssade, Florence Azaïs, Laurent Latorre, Francois Lefevre:
Low-cost functional test of a 2.4 GHz OQPSK transmitter using standard digital ATE. IOLTS 2018: 17-22 - [c74]Amit Karel, Florence Azaïs, Mariane Comte, Jean-Marc Gallière, Michel Renovell:
Impact of process variations on the detectability of resistive short defects: Comparative analysis between 28nm Bulk and FDSOI technologies. LATS 2018: 1-5 - 2017
- [c73]Amit Karel, Florence Azaïs, Mariane Comte, Jean-Marc Gallière, Michel Renovell, Keshav Singh:
Detection of resistive open and short defects in FDSOI under delay-based test: Optimal VDD and body biasing conditions. ETS 2017: 1-2 - [c72]Amit Karel, Florence Azaïs, Mariane Comte, Jean-Marc Gallière, Michel Renovell, Keshav Singh:
Comprehensive Study for Detection of Weak Resistive Open and Short Defects in FDSOI Technology. ISVLSI 2017: 320-325 - 2016
- [c71]Amit Karel, Mariane Comte, Jean-Marc Gallière, Florence Azaïs, Michel Renovell:
Impact of VT and Body-Biasing on Resistive Short Detection in 28nm UTBB FDSOI - LVT and RVT Configurations. ISVLSI 2016: 164-169 - [c70]Amit Karel, Mariane Comte, Jean-Marc Gallière, Florence Azaïs, Michel Renovell:
Comparative study of Bulk, FDSOI and FinFET technologies in presence of a resistive short defect. LATS 2016: 129-134 - 2015
- [c69]Florence Azaïs, Stephane David-Grignot, Laurent Latorre, Francois Lefevre:
Embedded Test Instrument for On-Chip Phase Noise Evaluation of Analog/IF Signals. DDECS 2015: 237-242 - [c68]Florence Azaïs:
Analog test: Why still "à la mode" after more than 25 years of research? ETS 2015: 1 - [c67]Stephane David-Grignot, Florence Azaïs, Laurent Latorre, Francois Lefevre:
A new technique for low-cost phase noise production testing from 1-bit signal acquisition. ETS 2015: 1-6 - [c66]Syhem Larguech, Florence Azaïs, Serge Bernard
A Framework for Efficient Implementation of Analog/RF Alternate Test with Model Redundancy. ISVLSI 2015: 621-626 - [c65]Vincent Kerzerho, Ludovic Guillaume-Sage, Florence Azaïs, Mariane Comte, Michel Renovell, Serge Bernard
Toward Adaptation of ADCs to Operating Conditions through On-chip Correction. ISVLSI 2015: 634-639 - [c64]Florence Azaïs, Stephane David-Grignot, Laurent Latorre, Francois Lefevre:
A digital technique for the evaluation of SSB phase noise of analog/RF signals. LATS 2015: 1-6 - [c63]Manuel J. Barragán, Gildas Léger
Special session: Hot topics: Statistical test methods. VTS 2015: 1-2 - 2014
- [c62]Haithem Ayari, Florence Azaïs, Serge Bernard, Mariane Comte, Vincent Kerzerho, Michel Renovell:
New implementions of predictive alternate analog/RF test with augmented model redundancy. DATE 2014: 1-4 - [c61]Martin Andraud
Solutions for the self-adaptation of communicating systems in operation. IOLTS 2014: 234-239 - [c60]Stephane David-Grignot, Florence Azaïs, Laurent Latorre, Francois Lefevre:
Low-cost phase noise testing of complex RF ICs using standard digital ATE. ITC 2014: 1-9 - [c59]Syhem Larguech, Florence Azaïs, Serge Bernard
Evaluation of indirect measurement selection strategies in the context of analog/RF alternate testing. LATW 2014: 1-6 - [c58]Stephane David-Grignot, Florence Azaïs, Laurent Latorre, Francois Lefevre:
Phase noise measurement on IF analog signals using standard digital ATE resources. NEWCAS 2014: 121-124 - 2013
- [c57]Jie Jiang, Marina Aparicio, Mariane Comte, Florence Azaïs, Michel Renovell, Ilia Polian:
MIRID: Mixed-Mode IR-Drop Induced Delay Simulator. Asian Test Symposium 2013: 177-182 - [c56]Haithem Ayari, Florence Azaïs, Serge Bernard
Implementing model redundancy in predictive alternate test to improve test confidence. ETS 2013: 1 - [c55]Marina Aparicio, Mariane Comte, Florence Azaïs, Michel Renovell, Jie Jiang, Ilia Polian, Bernd Becker
Pre-characterization procedure for a mixed mode simulation of IR-drop induced delays. LATW 2013: 1-6 - [c54]Mouhamadou Dieng, Mariane Comte, Serge Bernard
Accurate and efficient analytical electrical model of antenna for NFC applications. NEWCAS 2013: 1-4 - 2012
- [c53]Haithem Ayari, Florence Azaïs, Serge Bernard
Making predictive analog/RF alternate test strategy independent of training set size. ITC 2012: 1-9 - [c52]Ahmed Amine Rekik, Florence Azaïs, Frédérick Mailly
Design-for-manufacturability of MEMS convective accelerometers through adaptive electrical calibration strategy. LATW 2012: 1-6 - [c51]Florence Azaïs, Laurent Latorre:
Low-cost SNR estimation of analog signals using standard digital automated test equipment (ATE). NEWCAS 2012: 197-200 - [c50]Haithem Ayari, Florence Azaïs, Serge Bernard
Smart selection of indirect parameters for DC-based alternate RF IC testing. VTS 2012: 19-24 - 2011
- [c49]Ahmed Amine Rekik, Florence Azaïs, Norbert Dumas, Frédérick Mailly
An electrical test method for MEMS convective accelerometers: Development and evaluation. DATE 2011: 806-811 - [c48]Ahmed Amine Rekik, Florence Azaïs, Norbert Dumas, Frédérick Mailly
Test and calibration of MEMS convective accelerometers with a fully electrical setup. LATW 2011: 1-6 - 2010
- [c47]Nicolas Pous, Florence Azaïs, Laurent Latorre, Jochen Rivoir:
On the use of standard digital ATE for the analysis of RF signals. ETS 2010: 43-48 - [c46]Nicolas Pous, Florence Azaïs, Laurent Latorre, Pascal Nouet, Jochen Rivoir:
Experiments on the analysis of phase/frequency-modulated RF signals using digital tester channels. LATW 2010: 1-7 - 2009
- [c45]Nicolas Pous, Florence Azaïs, Laurent Latorre, Pascal Nouet
Exploiting Zero-Crossing for the Analysis of FM Modulated Analog/RF Signals Using Digital ATE. Asian Test Symposium 2009: 261-266 - [c44]Florence Azaïs, Yves Bertrand, Michel Renovell:
An analysis of the timing behavior of CMOS digital blocks under Simultaneous Switching Noise conditions. DDECS 2009: 158-163 - [c43]Vincent Kerzerho, Philippe Cauvet, Serge Bernard
A multi-converter DFT technique for complex SIP: Concepts and validation. ECCTD 2009: 747-750 - 2008
- [c42]Norbert Dumas, Florence Azaïs, Frédérick Mailly
A novel method for test and calibration of capacitive accelerometers with a fully electrical setup. DDECS 2008: 304-309 - [c41]Florence Azaïs, Laurent Larguier, Yves Bertrand, Michel Renovell:
On the Detection of SSN-Induced Logic Errors through On-Chip Monitoring. IOLTS 2008: 233-238 - 2007
- [c40]Florence Azaïs, Laurent Larguier, Michel Renovell:
Impact of Simultaneous Switching Noise on the Static behavior of Digital CMOS Circuits. ATS 2007: 239-244 - [c39]Vincent Kerzerho, Philippe Cauvet, Serge Bernard
"Analogue Network of Converters": A DFT Technique to Test a Complete Set of ADCs and DACs Embedded in a Complex SiP or SOC. ETS 2007: 211-216 - 2006
- [c38]Vincent Kerzerho, Philippe Cauvet, Serge Bernard
"Analogue Network of Converters": A DFT Technique to Test a Complete Set of ADCs and DACs Embedded in a Complex SiP or SOC. ETS 2006: 159-164 - 2005
- [c37]Frédérick Mailly
Towards on-line testing of MEMS using electro-thermal excitation. ETS 2005: 76-81 - [c36]Norbert Dumas, Florence Azaïs, Laurent Latorre, Pascal Nouet:
On-Chip Electro-Thermal Stimulus Generation for a MEMS-Based Magnetic Field Sensor. VTS 2005: 213-218 - [c35]Gustavo Pereira, Antonio Andrade Jr., Tiago R. Balen, Marcelo Lubaszewski, Florence Azaïs, Michel Renovell:
Testing the Interconnect Networks and I/O Resources of Field Programmable Analog Arrays. VTS 2005: 389-394 - 2004
- [c34]Antonio Zenteno, Víctor H. Champac, Michel Renovell, Florence Azaïs:
Analysis and Attenuation Proposal in Ground Bounce. Asian Test Symposium 2004: 460-463 - [c33]Norbert Dumas, Florence Azaïs, Laurent Latorre, Pascal Nouet:
Electrically-induced thermal stimuli for MEMS testing. ETS 2004: 60-65 - [c32]Tiago R. Balen, Antonio Andrade Jr., Florence Azaïs, Michel Renovell, Marcelo Lubaszewski:
Testing the Configurable Analog Blocks of Field Programmable Analog Arrays. ITC 2004: 893-902 - [c31]Tiago R. Balen, Antonio Andrade Jr., Florence Azaïs, Marcelo Lubaszewski, Michel Renovell:
An Approach to the Built-In Self-Test of Field Programmable Analog Arrays. VTS 2004: 383-388 - 2003
- [c30]Michel Renovell, Jean Marc Gallière, Florence Azaïs, Yves Bertrand:
Delay Testing of MOS Transistor with Gate Oxide Short. Asian Test Symposium 2003: 168-173 - [c29]Serge Bernard, Mariane Comte, Florence Azaïs, Yves Bertrand, Michel Renovell:
A New Methodology For ADC Test Flow Optimization. ITC 2003: 201-209 - 2002
- [c28]Yves Bertrand, Marie-Lise Flottes, Florence Azaïs, Serge Bernard
European Network for Test Education. DELTA 2002: 230-234 - [c27]Michel Renovell, Jean Marc Gallière, Florence Azaïs, Yves Bertrand:
Modeling gate oxide short defects in CMOS minimum transistors. ETW 2002: 15-20 - [c26]Serge Bernard
A high accuracy triangle-wave signal generator for on-chip ADC testing. ETW 2002: 89-94 - [c25]Florence Azaïs, Serge Bernard, Yves Bertrand, Mariane Comte, Michel Renovell, Marcelo Lubaszewski:
Estimating Static Parameters of A-to-D Converters from Spectral Analysis. LATW 2002: 174-179 - 2001
- [c24]Florence Azaïs, Serge Bernard
Implementation of a linear histogram BIST for ADCs. DATE 2001: 590-595 - [c23]Serge Bernard, Florence Azaïs, Yves Bertrand, Michel Renovell:
Analog BIST Generator for ADC Testing. DFT 2001: 338-346 - [c22]Florence Azaïs, Serge Bernard, Yves Bertrand, Michel Renovell:
On-chip Generator of a Saw-Tooth Test Stimulus for ADC BIST. VLSI-SOC 2001: 425-436 - [c21]Michel Renovell, Jean Marc Gallière, Florence Azaïs, Serge Bernard, Yves Bertrand:
Boolean and current detection of MOS transistor with gate oxide short. ITC 2001: 1039-1048 - [c20]Florence Azaïs, Serge Bernard, Yves Bertrand, Xavier Michel, Michel Renovell:
On-Chip Generation of High-Quality Ramp Stimulus With Minimal Silicon Area. LATW 2001: 112-117 - [c19]Michel Renovell, Jean Marc Gallière, Florence Azaïs, Yves Bertrand:
Electrical Analysis of Gate Oxide Short in MOS Technologies. LATW 2001: 266-272 - [c18]Florence Azaïs, Serge Bernard, Yves Bertrand, Xavier Michel, Michel Renovell:
A Low-Cost Adaptive Ramp Generator for Analog BIST Applications. VTS 2001: 266-271 - 2000
- [c17]Luigi Carro, Érika F. Cota, Marcelo Lubaszewski, Yves Bertrand, Florence Azaïs, Michel Renovell:
TI-BIST: a temperature independent analog BIST for switched-capacitor filters. Asian Test Symposium 2000: 78-83 - [c16]Érika F. Cota, Michel Renovell, Florence Azaïs, Yves Bertrand, Luigi Carro, Marcelo Lubaszewski:
Reuse of Existing Resources for Analog BIST of a Switch Capacitor Filte. DATE 2000: 226-230 - [c15]Florence Azaïs, Serge Bernard, Y. Betrand, Michel Renovell:
Towards an ADC BIST scheme using the histogram test technique. ETW 2000: 53-58 - [c14]Luigi Carro, Michel Renovell, Érika F. Cota, Marcelo Lubaszewski, Yves Bertrand, Florence Azaïs:
On the Temperature Dependencies of Analog BIST. LATW 2000: 88-93 - [c13]Serge Bernard, Florence Azaïs, Yves Bertrand, Michel Renovell:
Minimizing the Hardware Overhead of a Histogram-Based BIST Scheme for Analog-to-Digital Converters. LATW 2000: 118-122 - [c12]Michel Renovell, Florence Azaïs, Serge Bernard, Yves Bertrand:
Hardware Resource Minimization for Histogram-Based ADC BIST. VTS 2000: 247-254 - 1999
- [c11]Michel Renovell, Florence Azaïs, J.-C. Bodin, Yves Bertrand:
Functional and structural testing of switched-current circuits. ETW 1999: 22-27 - [c10]Michel Renovell, André Ivanov, Yves Bertrand, Florence Azaïs, Sumbal Rafiq:
Optimal conditions for Boolean and current detection of floating gate faults. ITC 1999: 477-486 - [c9]Yves Bertrand, Florence Azaïs, Marie-Lise Flottes, Regis Lorival:
A Successful Distance-Learning Experience for IC Test Education. MSE 1999: 20-21 - 1998
- [c8]Michel Renovell, Florence Azaïs, J.-C. Bodin, Yves Bertrand:
BISTing Switched-Current Circuits. Asian Test Symposium 1998: 372-377 - [c7]Florence Azaïs, André Ivanov, Michel Renovell, Yves Bertrand:
A Methodology and Design for Effective Testing of Voltage-Controlled Oscillators (VCOs. Asian Test Symposium 1998: 383-387 - [c6]Michel Renovell, Florence Azaïs, Yves Bertrand:
Optimized Implementations of the Multi-Configuration DFT Technique for Analog Circuits. DATE 1998: 815-821 - [c5]Marcelo Lubaszewski, Michel Renovell, Salvador Mir, Florence Azaïs, Yves Bertrand:
A Built-In Multi-Mode Stimuli Generator for Analogue and Mixed-Signal Testing. SBCCI 1998: 175-178 - [c4]Florence Azaïs, Michel Renovell, Yves Bertrand, J.-C. Bodin:
Design-For-Testability for Switched-Current Circuits. VTS 1998: 370-375 - 1997
- [c3]Michel Renovell, Florence Azaïs, Yves Bertrand:
On-chip analog output response compaction. ED&TC 1997: 568-572 - 1996
- [c2]Michel Renovell, Florence Azaïs, Yves Bertrand:
The multi-configuration: A DFT technique for analog circuits. VTS 1996: 54-59 - 1995
- [c1]Michel Renovell, Florence Azaïs, Yves Bertrand:
A design-for-test technique for multistage analog circuits. Asian Test Symposium 1995: 113-119
Informal and Other Publications
- 2024
- [i2]Muayad J. Aljafar, Florence Azaïs, Marie-Lise Flottes, Samuel Pagliarini:
Utilizing Layout Effects for Analog Logic Locking. CoRR abs/2401.06508 (2024) - 2022
- [i1]Muayad J. Aljafar
Leveraging Layout-based Effects for Locking Analog ICs. CoRR abs/2209.01856 (2022)
Coauthor Index
Jean-Marc Gallière
aka: Jean Marc Gallière
aka: Jean Marc Gallière
Vincent Kerzerho
aka: Vincent Kerzèrho
aka: Vincent Kerzèrho
[j41] [j39] [j35] [j33] [j32] [j31] [j29] [j25] [j24] [j23] [j20] [j19] [j18] [j17] [j16] [j14] [j13] [j11] [j10] [j9] [j8] [j7] [j6] [j5] [j4] [j3] [j2] [j1] [c74] [c73] [c72] [c71] [c70] [c66] [c65] [c62] [c61] [c59] [c57] [c56] [c55] [c54] [c53] [c50] [c44] [c43] [c41] [c40] [c39] [c38] [c35] [c34] [c32] [c31] [c30] [c29] [c27] [c26] [c25] [c24] [c23] [c22] [c21] [c20] [c19] [c18] [c17] [c16] [c15] [c14] [c13] [c12] [c11] [c10] [c8] [c7] [c6] [c5] [c4] [c3] [c2] [c1]
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