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Philippe Flatresse
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2020 – today
- 2021
- [c20]Yasser Moursy, Thiago Raupp da Rosa, Lionel Jure, Anthony Quelen, Sébastien Genevey, Lionel Pierrefeu, Emmanuel G. Collins Jr., Joerg Winkler, Jonathan Park, Gaël Pillonnet
, Vincent Huard, Andrea Bonzo, Philippe Flatresse:
A 0.021mm2 PVT-Aware Digital-Flow-Compatible Adaptive Back-Biasing Regulator with Scalable Drivers Achieving 450% Frequency Boosting and 30% Power Reduction in 22nm FDSOI Technology. ISSCC 2021: 492-494 - 2020
- [j11]Alfio Di Mauro, Davide Rossi
Performance-aware predictive-model-based on-chip body-bias regulation strategy for an ULP multi-core cluster in 28 nm UTBB FD-SOI. Integr. 72: 194-207 (2020) - [i2]Alfio Di Mauro, Davide Rossi, Antonio Pullini, Philippe Flatresse, Luca Benini:
Performance-Aware Predictive-Model-Based On-Chip Body-Bias Regulation Strategy for an ULP Multi-Core Cluster in 28nm UTBB FD-SOI. CoRR abs/2007.13667 (2020)
2010 – 2019
- 2018
- [c19]Souhir Mhira, Vincent Huard, D. Arora, Philippe Flatresse, Alain Bravaix
Resilient automotive products through process, temperature and aging compensation schemes. IRPS 2018: 3 - [c18]Alfio Di Mauro, Davide Rossi, Antonio Pullini, Philippe Flatresse, Luca Benini
Live Demonstration: Body-Bias Based Performance Monitoring and Compensation for a Near-Threshold Multi-Core Cluster in 28nm FD-SOI Technology. ISCAS 2018: 1- - [c17]Anthony Quelen, Gaël Pillonnet
A 2.5μW 0.0067mm2 automatic back-biasing compensation unit achieving 50% leakage reduction in FDSOI 28nm over 0.35-to-1V VDD range. ISSCC 2018: 304-306 - 2017
- [j10]Davide Rossi
A Self-Aware Architecture for PVT Compensation and Power Nap in Near Threshold Processors. IEEE Des. Test 34(6): 46-53 (2017) - [j9]Pascal Giard
PolarBear: A 28-nm FD-SOI ASIC for Decoding of Polar Codes. IEEE J. Emerg. Sel. Topics Circuits Syst. 7(4): 616-629 (2017) - [j8]Davide Rossi, Antonio Pullini, Igor Loi, Michael Gautschi, Frank Kagan Gürkaynak, Adam Teman
Energy-Efficient Near-Threshold Parallel Computing: The PULPv2 Cluster. IEEE Micro 37(5): 20-31 (2017) - [j7]Andrea Bonetti
Multipliers-Driven Perturbation of Coefficients for Low-Power Operation in Reconfigurable FIR Filters. IEEE Trans. Circuits Syst. I Regul. Pap. 64-I(9): 2388-2400 (2017) - [j6]Anuj Grover
A 32 kb 0.35-1.2 V, 50 MHz-2.5 GHz Bit-Interleaved SRAM With 8 T SRAM Cell and Data Dependent Write Assist in 28-nm UTBB-FDSOI CMOS. IEEE Trans. Circuits Syst. I Regul. Pap. 64-I(9): 2438-2447 (2017) - [c16]Alfio Di Mauro, Davide Rossi, Antonio Pullini, Philippe Flatresse, Luca Benini:
Temperature and process-aware performance monitoring and compensation for an ULP multi-core cluster in 28nm UTBB FD-SOI technology. PATMOS 2017: 1-8 - [i1]Pascal Giard, Alexios Balatsoukas-Stimming, Thomas Christoph Müller, Andrea Bonetti, Claude Thibeault, Warren J. Gross, Philippe Flatresse, Andreas Burg:
PolarBear: A 28-nm FD-SOI ASIC for Decoding of Polar Codes. CoRR abs/1708.09603 (2017) - 2016
- [j5]Brian Zimmer, Yunsup Lee, Alberto Puggelli, Jaehwa Kwak, Ruzica Jevtic
A RISC-V Vector Processor With Simultaneous-Switching Switched-Capacitor DC-DC Converters in 28 nm FDSOI. IEEE J. Solid State Circuits 51(4): 930-942 (2016) - [c15]Davide Rossi
193 MOPS/mW @ 162 MOPS, 0.32V to 1.15V voltage range multi-core accelerator for energy efficient parallel and sequential digital processing. COOL Chips 2016: 1-3 - [c14]Milovan Blagojevic, Martin Cochet, Ben Keller, Philippe Flatresse, Andrei Vladimirescu, Borivoje Nikolic
A fast, flexible, positive and negative adaptive body-bias generator in 28nm FDSOI. VLSI Circuits 2016: 1-2 - 2015
- [j4]Edith Beigné
A 460 MHz at 397 mV, 2.6 GHz at 1.3 V, 32 bits VLIW DSP Embedding F MAX Tracking. IEEE J. Solid State Circuits 50(1): 125-136 (2015) - [c13]Davide Rossi
PULP: A parallel ultra low power platform for next generation IoT applications. Hot Chips Symposium 2015: 1-39 - [c12]Brian Zimmer, Yunsup Lee, Alberto Puggelli, Jaehwa Kwak, Ruzica Jevtic
A RISC-V vector processor with tightly-integrated switched-capacitor DC-DC converters in 28nm FDSOI. VLSIC 2015: 316- - 2014
- [j3]David Jacquet, Frederic Hasbani, Philippe Flatresse, Robin Wilson, Franck Arnaud, Giorgio Cesana, Thierry Di Gilio, Christophe Lecocq, Tanmoy Roy, Amit Chhabra, Chiranjeev Grover, Olivier Minez, Jacky Uginet, Guy Durieu, Cyril Adobati, Davide Casalotto, Frederic Nyer, Patrick Menut, Andreia Cathelin, Indavong Vongsavady, Philippe Magarshack:
A 3 GHz Dual Core Processor ARM Cortex TM -A9 in 28 nm UTBB FD-SOI CMOS With Ultra-Wide Voltage Range and Energy Efficiency Optimization. IEEE J. Solid State Circuits 49(4): 812-826 (2014) - [c11]Philippe Flatresse:
Process and design solutions for exploiting FD-SOI technology towards energy efficient SOCs. ISLPED 2014: 127-130 - [c10]Robin Wilson, Edith Beigné
27.1 A 460MHz at 397mV, 2.6GHz at 1.3V, 32b VLIW DSP, embedding FMAX tracking. ISSCC 2014: 452-453 - [c9]Matthew Weiner, Milovan Blagojevic, Sergey Skotnikov, Andreas Burg
27.7 A scalable 1.5-to-6Gb/s 6.2-to-38.1mW LDPC decoder for 60GHz wireless networks in 28nm UTBB FDSOI. ISSCC 2014: 464-465 - 2013
- [c8]Edith Beigné, Alexandre Valentian, Bastien Giraud, Olivier Thomas, Thomas Benoist, Yvain Thonnart, Serge Bernard, Guillaume Moritz, Olivier Billoint, Y. Maneglia, Philippe Flatresse, Jean-Philippe Noel, Fady Abouzeid
Ultra-wide voltage range designs in fully-depleted silicon-on-insulator FETs. DATE 2013: 613-618 - [c7]Philippe Magarshack, Philippe Flatresse, Giorgio Cesana:
UTBB FD-SOI: a process/design symbiosis for breakthrough energy-efficiency. DATE 2013: 952-957 - [c6]Kaya Can Akyel, Lorenzo Ciampolini, Olivier Thomas, Bertrand Pelloux-Prayer, Shishir Kumar, Philippe Flatresse, Christophe Lecocq, Gérard Ghibaudo:
Multiple-pulse dynamic stability and failure analysis of low-voltage 6T-SRAM bitcells in 28nm UTBB-FDSOI. ISCAS 2013: 1452-1455 - [c5]Philippe Flatresse, Bastien Giraud, Jean-Philippe Noel, Bertrand Pelloux-Prayer, Fabien Giner, Deepak-Kumar Arora, Franck Arnaud, Nicolas Planes, Julien Le Coz, Olivier Thomas, Sylvain Engels, Giorgio Cesana, Robin Wilson, Pascal Urard:
Ultra-wide body-bias range LDPC decoder in 28nm UTBB FDSOI technology. ISSCC 2013: 424-425 - [c4]Bertrand Pelloux-Prayer, Alexandre Valentian, Bastien Giraud, Yvain Thonnart
Fine grain multi-VT co-integration methodology in UTBB FD-SOI technology. VLSI-SoC 2013: 168-173 - 2012
- [j2]Smriti Joshi, Anne Lombardot, Philippe Flatresse, Carmelo D'Agostino
Statistical Estimation of Dominant Physical Parameters for Leakage Variability in 32 Nanometer CMOS, Under Supply Voltage Variations. J. Low Power Electron. 8(1): 113-124 (2012) - 2011
- [c3]N. Ruiz Amador, Vincent Huard, E. Pion, Florian Cacho, Damien Croain, V. Robert, Sylvain Engels, Philippe Flatresse, Lorena Anghel
Bottom-up digital system-level reliability modeling. CICC 2011: 1-4 - [c2]Julien Le Coz, Philippe Flatresse, Sylvain Engels, Alexandre Valentian, Marc Belleville, Christine Raynaud, Damien Croain, Pascal Urard:
Comparison of 65nm LP bulk and LP PD-SOI with adaptive power gate body bias for an LDPC codec. ISSCC 2011: 336-337
2000 – 2009
- 2006
- [j1]Christophe Entringer, Philippe Flatresse, Philippe Galy, Florence Azaïs, Pascal Nouet
Electro-thermal short pulsed simulation for SOI technology. Microelectron. Reliab. 46(9-11): 1482-1485 (2006) - 2002
- [c1]Mario R. Casu
Converting an Embedded Low-Power SRAM from Bulk to PD-SOI. MTDT 2002: 163-167
Coauthor Index
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