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José Pineda de Gyvez
José de Jesus Pineda de Gyvez
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- affiliation: Eindhoven University of Technology, Netherlands
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2020 – today
- 2023
- [j45]Shima Sedighiani
, Kamlesh Singh, Roel Jordans, Pieter Harpe
A 380 fW Leakage Data Retention Flip-Flop for Short Sleep Periods. IEEE Trans. Circuits Syst. II Express Briefs 70(7): 2650-2654 (2023) - 2021
- [j44]Barry de Bruin
Multi-Level Optimization of an Ultra-Low Power BrainWave System for Non-Convulsive Seizure Detection. IEEE Trans. Biomed. Circuits Syst. 15(5): 1107-1121 (2021) - [j43]Kamlesh Singh
Twenty Years of Near/Sub-Threshold Design Trends and Enablement. IEEE Trans. Circuits Syst. II Express Briefs 68(1): 5-11 (2021) - [j42]Kamlesh Singh
Converter-Free Power Delivery Using Voltage Stacking for Near/Subthreshold Operation. IEEE Trans. Very Large Scale Integr. Syst. 29(6): 1039-1051 (2021) - [c82]Shima Sedighiani, Kamlesh Singh, Roel Jordans, Pieter Harpe, José Pineda de Gyvez:
A Low Power Fully-Digital Multi-Level Voltage Monitor Operating in a Wide Voltage Range for Energy Harvesting IoT. ISQED 2021: 13-18 - 2020
- [j41]Emad A. Ibrahim
Multi-Angle Fusion for Low-Cost Near-Field Ultrasonic in-Air Gesture Recognition. IEEE Access 8: 191204-191218 (2020) - [j40]Hamed Fatemi, Andrew B. Kahng, Hyein Lee
Heuristic Methods for Fine-Grain Exploitation of FDSOI. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(10): 2860-2871 (2020) - [c81]Emad A. Ibrahim, Marc Geilen
Low Complexity Multi-directional In-Air Ultrasonic Gesture Recognition Using a TCN. DATE 2020: 1259-1264 - [c80]Paul Detterer
Trading Sensitivity for Power in an IEEE 802.15.4 Conformant Adequate Demodulator. DATE 2020: 1674-1679 - [c79]Shima Sedighiani, Kamlesh Singh, Jos Huisken
An Electromagnetic Energy Harvester and Power Management in 28-nm FDSOI for IoT. MECO 2020: 1-5 - [c78]Hamed Fatemi, Andrew B. Kahng, Minsoo Kim, José Pineda de Gyvez:
Optimal bounded-skew steiner trees to minimize maximum k-active dynamic power. SLIP 2020: 12
2010 – 2019
- 2019
- [j39]Hamed Fatemi, Andrew B. Kahng, Hyein Lee, Jiajia Li, José Pineda de Gyvez:
Enhancing sensitivity-based power reduction for an industry IC design context. Integr. 66: 96-111 (2019) - [j38]P. Anagnostou, Andres Gomez
Energy and power awareness in hardware schedulers for energy harvesting IoT SoCs. Integr. 67: 33-43 (2019) - [j37]Massimo Alioto, Magdy S. Abadir, Tughrul Arslan, Chirn Chye Boon, Andreas Burg
Editorial TVLSI Positioning - Continuing and Accelerating an Upward Trajectory. IEEE Trans. Very Large Scale Integr. Syst. 27(2): 253-280 (2019) - [j36]Hadi Ahmadi Balef
Timing Speculation With Optimal In Situ Monitoring Placement and Within-Cycle Error Prevention. IEEE Trans. Very Large Scale Integr. Syst. 27(5): 1206-1217 (2019) - [c77]Paul Detterer
Trading Digital Accuracy for Power in an RSSI Computation of a Sensor Network Transceiver. DATE 2019: 102-107 - [c76]Hadi Ahmadi Balef, Kees Goossens, José Pineda de Gyvez:
Chip Health Tracking Using Dynamic In-Situ Delay Monitoring. DATE 2019: 304-307 - [c75]Emad A. Ibrahim, Jos Huisken
Keyword Spotting using Time-Domain Features in a Temporal Convolutional Network. DSD 2019: 313-319 - [c74]Emad A. Ibrahim, Min Li, José Pineda de Gyvez:
PRESS/HOLD/RELEASE Ultrasonic Gestures and Low Complexity Recognition Based on TCN. SiPS 2019: 172-177 - [c73]Kamlesh Singh, Barry de Bruin
Voltage Stacked Design of a Microcontroller for Near/Sub-threshold Operation. SoCC 2019: 370-375 - 2018
- [j35]Xun Jiao
CLIM: A Cross-Level Workload-Aware Timing Error Prediction Model for Functional Units. IEEE Trans. Computers 67(6): 771-783 (2018) - [c72]Hadi Ahmadi Balef, Hamed Fatemi, Kees Goossens, José Pineda de Gyvez:
Effective In-Situ Chip Health Monitoring with Selective Monitor Insertion Along Timing Paths. ACM Great Lakes Symposium on VLSI 2018: 213-218 - [c71]Kamlesh Singh, Omar Alejandro Rodriguez Rosas, Hailong Jiao, Jos Huisken
Multi-Bit Pulsed-Latch Based Low Power Synchronous Circuit Design. ISCAS 2018: 1-5 - [c70]Kamlesh Singh, Hailong Jiao, Jos Huisken
Low power latch based design with smart retiming. ISQED 2018: 329-334 - [c69]P. Anagnostou, Andres Gomez, Pascal A. Hager, Hamed Fatemi, José Pineda de Gyvez, Lothar Thiele, Luca Benini
Torpor: A Power-Aware HW Scheduler for Energy Harvesting IoT SoCs. PATMOS 2018: 54-61 - 2017
- [j34]Kristof Blutman
A Low-Power Microcontroller in a 40-nm CMOS Using Charge Recycling. IEEE J. Solid State Circuits 52(4): 950-960 (2017) - [j33]Andres Gomez
Increasing the energy efficiency of microcontroller platforms with low-design margin co-processors. Microprocess. Microsystems 53: 213-228 (2017) - [j32]Kristof Blutman, Hamed Fatemi, Ajay Kapoor, Andrew B. Kahng, Jiajia Li
Logic Design Partitioning for Stacked Power Domains. IEEE Trans. Very Large Scale Integr. Syst. 25(11): 3045-3056 (2017) - [c68]Kristof Blutman, Hamed Fatemi, Andrew B. Kahng, Ajay Kapoor, Jiajia Li, José Pineda de Gyvez:
Floorplan and placement methodology for improved energy reduction in stacked power-domain design. ASP-DAC 2017: 444-449 - [c67]Pascal Alexander Hager, Hamed Fatemi, José Pineda de Gyvez, Luca Benini
A scan-chain based state retention methodology for IoT processors operating on intermittent energy. DATE 2017: 1171-1176 - [c66]Hadi Ahmadi Balef, Hailong Jiao, José Pineda de Gyvez, Kees Goossens:
An analytical model for interdependent setup/hold-time characterization of flip-flops. ISQED 2017: 209-214 - [c65]Martin Van Leussen, Jos Huisken
Reconfigurable Support Vector Machine Classifier with Approximate Computing. ISVLSI 2017: 13-18 - 2016
- [c64]Kristof Blutman, Ajay Kapoor, Jacinto Garcia Martinez, Hamed Fatemi, José Pineda de Gyvez:
Lower power by voltage stacking: a fine-grained system design approach. DAC 2016: 78:1-78:5 - [c63]José Pineda de Gyvez, Hamed Fatemi, Maarten Vertregt:
Circuit valorization in the IC design ecosystem. ICCAD 2016: 25 - [c62]Kristof Blutman, Ajay Kapoor, Arjun Majumdar, Jacinto Garcia Martinez, Juan Diego Echeverri, Leo Sevat, Arnoud P. van der Wel, Hamed Fatemi, José Pineda de Gyvez, Kofi A. A. Makinwa:
A microcontroller with 96% power-conversion efficiency using stacked voltage domains. VLSI Circuits 2016: 1-2 - 2015
- [j31]Yanxiang Huang, Ajay Kapoor, Robert Rutten, José Pineda de Gyvez:
A 13 bits 4.096 GHz 45 nm CMOS digital decimation filter chain with Carry-Save format numbers. Microprocess. Microsystems 39(8): 869-878 (2015) - [j30]Andrew B. Kahng, Seokhyeong Kang, Jiajia Li, José Pineda de Gyvez:
An Improved Methodology for Resilient Design Implementation. ACM Trans. Design Autom. Electr. Syst. 20(4): 66:1-66:26 (2015) - [c61]Andres Gomez, Christian Pinto, Andrea Bartolini, Davide Rossi, Luca Benini, Hamed Fatemi, José Pineda de Gyvez:
Reducing energy consumption in microcontroller-based platforms with low design margin co-processors. DATE 2015: 269-272 - [c60]Xun Jiao, Abbas Rahimi
Supervised learning based model for predicting variability-induced timing errors. NEWCAS 2015: 1-4 - [c59]Mini Jayakrishnan
Slack-aware timing margin redistribution technique utilizing error avoidance flip-flops and time borrowing. VLSI-SoC 2015: 159-164 - 2014
- [j29]Ajay Kapoor, Cas Groot, Gerard Villar Pique, Hamed Fatemi, Juan Diego Echeverri, Leo Sevat, Maarten Vertregt, Maurice Meijer, Vibhu Sharma, Yu Pu, José Pineda de Gyvez:
Digital Systems Power Management for High Performance Mixed Signal Platforms. IEEE Trans. Circuits Syst. I Regul. Pap. 61-I(4): 961-975 (2014) - [c58]Sebastien Fabrie, Juan Diego Echeverri, Maarten Vertregt, José Pineda de Gyvez:
Standard cell library tuning for variability tolerant designs. DATE 2014: 1-6 - [c57]Yu Pu, Juan Diego Echeverri, Maurice Meijer, José Pineda de Gyvez:
Logic synthesis of low-power ICs with ultra-wide voltage and frequency scaling. DATE 2014: 1-2 - [c56]Bo Liu, Maryam Ashouei, Tobias Gemmeke
Sub-threshold custom standard cell library validation. ISQED 2014: 257-262 - 2013
- [j28]Hamid Reza Pourshaghaghi, José Pineda de Gyvez:
Fuzzy-Controlled Voltage Scaling Based on Supply Current Tracking. IEEE Trans. Computers 62(12): 2397-2410 (2013) - [j27]Ajay Kapoor, José Pineda de Gyvez:
Architectural Analysis for Wirelessly Powered Computing Platforms. IEEE Trans. Very Large Scale Integr. Syst. 21(11): 2106-2117 (2013) - [c55]Yanxiang Huang, Ajay Kapoor, Robert Rutten, José Pineda de Gyvez:
A 13 bits 4.096 GHz 45 nm CMOS digital decimation filter chain using Carry-Save format numbers. NORCHIP 2013: 1-4 - 2012
- [j26]Amir Zjajo, Manuel J. Barragan Asian, José Pineda de Gyvez:
Digital Adaptive Calibration of Multi-Step Analog to Digital Converters. J. Low Power Electron. 8(2): 182-196 (2012) - [j25]Amir Zjajo, Manuel J. Barragan Asian, José Pineda de Gyvez:
Low-Power Die-Level Process Variation and Temperature Monitors for Yield Analysis and Optimization in Deep-Submicron CMOS. IEEE Trans. Instrum. Meas. 61(8): 2212-2221 (2012) - [j24]Maurice Meijer, José Pineda de Gyvez:
Body-Bias-Driven Design Strategy for Area- and Performance-Efficient CMOS Circuits. IEEE Trans. Very Large Scale Integr. Syst. 20(1): 42-51 (2012) - [c54]Bo Liu, Maryam Ashouei, Jos Huisken
Standard cell sizing for subthreshold operation. DAC 2012: 962-967 - [c53]Hamid Reza Pourshaghaghi, Hamed Fatemi, José Pineda de Gyvez:
Sliding-Mode Control to Compensate PVT Variations in dual core systems. DATE 2012: 1048-1053 - [c52]Sebastian M. Londono, José Pineda de Gyvez:
A better-than-worst-case circuit design methodology using timing-error speculation and frequency adaptation. SoCC 2012: 15-20 - 2011
- [j23]Amir Zjajo, Qin Tang, Michel Berkelaar, José Pineda de Gyvez, Alessandro Di Bucchianico
Stochastic Analysis of Deep-Submicrometer CMOS Process for Reliable Circuits Designs. IEEE Trans. Circuits Syst. I Regul. Pap. 58-I(1): 164-175 (2011) - [c51]Bo Liu, Hamid Reza Pourshaghaghi, Sebastian M. Londono, José Pineda de Gyvez:
Process Variation Reduction for CMOS Logic Operating at Sub-threshold Supply Voltage. DSD 2011: 135-139 - [c50]Amir Zjajo, José Pineda de Gyvez:
A 1.2v 55mW 12bits self-calibrated dual-residue analog to digital converter in 90 nm CMOs. ISLPED 2011: 187-192 - 2010
- [j22]Maurice Meijer, José Pineda de Gyvez, Ajay Kapoor:
Ultra-Low-Power Digital Design with Body Biasing for Low Area and Performance-Efficient Operation. J. Low Power Electron. 6(4): 521-532 (2010) - [j21]Yu Pu, José de Jesus Pineda de Gyvez, Henk Corporaal, Yajun Ha:
An Ultra-Low-Energy Multi-Standard JPEG Co-Processor in 65 nm CMOS With Sub/Near Threshold Supply Voltage. IEEE J. Solid State Circuits 45(3): 668-680 (2010) - [c49]Hamid Reza Pourshaghaghi, José Pineda de Gyvez:
Power-performance optimization using fuzzy control of simultaneous supply voltage and body biasing scaling. ICECS 2010: 281-284 - [c48]Maurice Meijer, José Pineda de Gyvez, Ben Kup, Bert van Uden, Peter Bastiaansen, Marco Lammers, Maarten Vertregt:
A forward body bias generator for digital CMOS circuits with supply voltage scaling. ISCAS 2010: 2482-2485 - [c47]Maurice Meijer, José Pineda de Gyvez:
Body bias driven design synthesis for optimum performance per area. ISQED 2010: 472-477
2000 – 2009
- 2009
- [j20]Amir Zjajo, José Pineda de Gyvez:
Analog Automatic Test Pattern Generation for Quasi-Static Structural Test. IEEE Trans. Very Large Scale Integr. Syst. 17(10): 1383-1391 (2009) - [c46]Sebastian M. Londono, José Pineda de Gyvez:
An energy-aware multiplier based on a Configurable-Reuse of points design methodology. ICECS 2009: 89-92 - [c45]Hamid Reza Pourshaghaghi, José Pineda de Gyvez:
Dynamic voltage scaling based on supply current tracking using fuzzy Logic controller. ICECS 2009: 779-782 - [c44]Yu Pu, José de Jesus Pineda de Gyvez, Henk Corporaal, Yajun Ha:
An ultra-low-energy/frame multi-standard JPEG co-processor in 65nm CMOS with sub/near-threshold power supply. ISSCC 2009: 146-147 - 2008
- [c43]Yu Pu, José de Jesus Pineda de Gyvez, Henk Corporaal, Yajun Ha:
Statistical noise margin estimation for sub-threshold combinational circuits. ASP-DAC 2008: 176-179 - [c42]Amir Zjajo, José Pineda de Gyvez:
Diagnostic Analysis of Static Errors in Multi-Step Analog to Digital Converters. DATE 2008: 74-79 - [c41]Amir Zjajo, Shaji Krishnan, José Pineda de Gyvez:
Efficient Estimation of Die-Level Process Parameter Variations via the EM-Algorithm. DDECS 2008: 287-292 - [c40]Amir Zjajo, José Pineda de Gyvez:
Calibration and Debugging of Multi-step Analog to Digital Converters. DELTA 2008: 512-515 - 2007
- [j19]Sandeep Kumar Goel, Maurice Meijer, José Pineda de Gyvez:
Efficient testing and diagnosis of faulty power switches in SOCs. IET Comput. Digit. Tech. 1(3): 230-236 (2007) - [c39]Amir Zjajo, Manuel J. Barragan Asian, José Pineda de Gyvez:
Interactive presentation: BIST method for die-level process parameter variation monitoring in analog/mixed-signal integrated circuits. DATE 2007: 1301-1306 - [c38]Yu Pu, José de Jesus Pineda de Gyvez, Henk Corporaal, Yajun Ha:
Vt balancing and device sizing towards high yield of sub-threshold static logic gates. ISLPED 2007: 355-358 - 2006
- [j18]Amir Zjajo, José Pineda de Gyvez, Guido Gronthoud:
Structural Fault Modeling and Fault Detection Through Neyman-Pearson Decision Criteria for Analog Integrated Circuits. J. Electron. Test. 22(4-6): 399-409 (2006) - [j17]Josep Rius, Maurice Meijer, José Pineda de Gyvez:
An Activity Monitor for Power/Performance Tuning of CMOS Digital Circuits. J. Low Power Electron. 2(1): 80-86 (2006) - [j16]Andrei Pavlov, Manoj Sachdev, José Pineda de Gyvez:
Weak Cell Detection in Deep-Submicron SRAMs: A Programmable Detection Technique. IEEE J. Solid State Circuits 41(10): 2334-2343 (2006) - [c37]Sandeep Kumar Goel, Maurice Meijer, José Pineda de Gyvez:
Testing and Diagnosis of Power Switches in SOCs. ETS 2006: 145-150 - 2005
- [j15]José Pineda de Gyvez, Guido Gronthoud, Rashid Amine:
Multi-VDD Testing for Analog Circuits. J. Electron. Test. 21(3): 311-322 (2005) - [j14]Wei Zhuo, Xiaoyong Li, Sudip Shekhar, Sherif H. K. Embabi, José Pineda de Gyvez, David J. Allstot, Edgar Sánchez-Sinencio:
A capacitor cross-coupled common-gate low-noise amplifier. IEEE Trans. Circuits Syst. II Express Briefs 52-II(12): 875-879 (2005) - [c36]Andrei Pavlov, Manoj Sachdev, José Pineda de Gyvez, Mohamed Azimane:
Programmable techniques for cell stability test and debug in embedded SRAMs. CICC 2005: 443-446 - [c35]Amir Zjajo, José Pineda de Gyvez:
Evaluation of signature-based testing of RF/analog circuits. ETS 2005: 62-67 - [c34]Maurice Meijer, Francesco Pessolano, José Pineda de Gyvez:
Limits to performance spread tuning using adaptive voltage and body biasing. ISCAS (1) 2005: 5-8 - [c33]Maurice Meijer, Francesco Pessolano, José Pineda de Gyvez:
Glitch-free discretely programmable clock generation on chip. ISCAS (2) 2005: 1839-1842 - [c32]Maurice Meijer, José Pineda de Gyvez, Ralph Otten:
On-chip digital power supply control for system-on-chip applications. ISLPED 2005: 311-314 - [c31]Amir Zjajo, Henk Jan Bergveld
Power-scan chain: design for analog testability. ITC 2005: 8 - [c30]Estella Silva, José Pineda de Gyvez, Guido Gronthoud:
Functional vs. multi-VDD testing of RF circuits. ITC 2005: 9 - [c29]Andrei Pavlov, Mohamed Azimane, José Pineda de Gyvez, Manoj Sachdev:
Word line pulsing technique for stability fault detection in SRAM cells. ITC 2005: 10 - [c28]Josep Rius, José Pineda de Gyvez, Maurice Meijer:
An Activity Monitor for Power/Performance Tuning of CMOS Digital Circuits. PATMOS 2005: 187-196 - 2004
- [j13]José Pineda de Gyvez, Hans Tuinhout:
Threshold voltage mismatch and intra-die leakage current in digital CMOS circuits. IEEE J. Solid State Circuits 39(1): 157-168 (2004) - [j12]Josep Rius Vázquez, José Pineda de Gyvez:
Built-in current sensor for ΔIDDQ testing. IEEE J. Solid State Circuits 39(3): 511-518 (2004) - [c27]Josep Rius Vázquez, José Pineda de Gyvez:
Power Supply Noise Monitor for Signal Integrity Faults. DATE 2004: 1406-1407 - [c26]Rohini Krishnan, José Pineda de Gyvez, Martijn T. Bennebroek:
Low energy FPGA interconnect design. FPGA 2004: 255 - [c25]Rohini Krishnan, José Pineda de Gyvez, Martijn T. Bennebroek:
Low energy FPGA interconnect design. ACM Great Lakes Symposium on VLSI 2004: 393-396 - [c24]Maurice Meijer, Francesco Pessolano, José Pineda de Gyvez:
Technology exploration for adaptive power and frequency scaling in 90nm CMOS. ISLPED 2004: 14-19 - [c23]José Pineda de Gyvez, Guido Gronthoud, Cristiano Cenci, Martin Posch, Thomas Burger, Manfred Koller:
Power Supply Ramping for Quasi-static Testing of PLLs. ITC 2004: 980-987 - [c22]Andrei Pavlov, Manoj Sachdev, José Pineda de Gyvez:
AN SRAM Weak Cell Fault Model and a DFT Technique with a Programmable Detection Threshold. ITC 2004: 1006-1015 - [c21]Rohini Krishnan, José Pineda de Gyvez:
Low Energy Switch Block For FPGAs. VLSI Design 2004: 209-214 - [c20]Josep Rius Vázquez, José Pineda de Gyvez:
Built-in Current Sensor for ?I{DDQ} Testing of Deep Submicron Digital CMOS ICs. VTS 2004: 53-58 - 2003
- [j11]Phillip Christie, José Pineda de Gyvez:
Prelayout interconnect yield prediction. IEEE Trans. Very Large Scale Integr. Syst. 11(1): 55-59 (2003) - [c19]Daniel Arumí-Delgado
Process-variability aware delay fault testing of ΔVT and weak-open defects. ETW 2003: 85-90 - [c18]Rohini Krishnan, José Pineda de Gyvez, Harry J. M. Veendrick:
Encoded-Low Swing Technique for Ultra Low Power Interconnect. FPL 2003: 240-251 - [c17]José Pineda de Gyvez, Guido Gronthoud, Rashid Amine:
VDD Ramp Testing for RF Circuits. ITC 2003: 651-658 - [c16]Antonio F. Mondragón-Torres, Terry Mayhugh Jr., José Pineda de Gyvez, José Silva-Martínez, Edgar Sánchez-Sinencio:
An Analog Integrated Circuit Design Laboratory. MSE 2003: 91-92 - [c15]José Pineda de Gyvez, Rosa Rodríguez-Montañés:
Threshold Voltage Mismatch (DeltaVT) Fault Modeling. VTS 2003: 145-150 - 2002
- [j10]Rosa Rodríguez-Montañés, Paul Volf, José Pineda de Gyvez:
Resistance Characterization for Weak Open Defects. IEEE Des. Test Comput. 19(5): 18-26 (2002) - 2001
- [c14]José Pineda de Gyvez:
Yield modeling and BEOL fundamentals. SLIP 2001: 135-163 - [c13]Phillip Christie, José Pineda de Gyvez:
Pre-layout prediction of interconnect manufacturability. SLIP 2001: 167-173 - [c12]José Pineda de Gyvez, Eric van de Wetering:
Average Leakage Current Estimation of CMOS Logic Circuits. VTS 2001: 375-379 - 2000
- [j9]Jiming Yin, José Pineda de Gyvez, Mi Lu:
Real-time wavelet-integrated corrosion detection system for casing pipes. Integr. Comput. Aided Eng. 7(2): 155-168 (2000) - [j8]Gabriele Manganaro, José Pineda de Gyvez:
Nonlinear Computability Based on Chaos. Int. J. Bifurc. Chaos 10(2): 415-430 (2000) - [j7]Jiming Yin, Mi Lu, José Pineda de Gyvez:
Full-signature real-time corrosion detection of underground casing pipes. IEEE Trans. Instrum. Meas. 49(1): 120-128 (2000) - [c11]Madhuban Kishor, José Pineda de Gyvez:
Threshold Voltage and Power-Supply Tolerance of CMOS Logic Design Families. DFT 2000: 349-357
1990 – 1999
- 1999
- [j6]Oscar Moreira-Tamayo, José Pineda de Gyvez:
Subband coding and image compression using CNN. Int. J. Circuit Theory Appl. 27(1): 135-151 (1999) - [c10]Octavio A. González, Gunhee Han, José Pineda de Gyvez, Edgar Sánchez-Sinencio:
CMOS cryptosystem using a Lorenz chaotic oscillator. ISCAS (5) 1999: 442-445 - [c9]A. Dornbusch, José Pineda de Gyvez:
Chaotic generation of PN sequences: a VLSI implementation. ISCAS (5) 1999: 454-457 - 1998
- [j5]Lei Wang, José Pineda de Gyvez, Edgar Sánchez-Sinencio:
Time multiplexed color image processing based on a CNN with cell-state outputs. IEEE Trans. Very Large Scale Integr. Syst. 6(2): 314-322 (1998) - 1996
- [j4]Apollo Q. Fong, Ajay Kanji, José Pineda de Gyvez:
Time-Multiplexing Scheme for Cellular Neural Networks Based Image Processing. Real Time Imaging 2(4): 231-239 (1996) - [j3]Chi-Chien Lee, José Pineda de Gyvez:
Color image processing in a cellular neural-network environment. IEEE Trans. Neural Networks 7(5): 1086-1098 (1996) - [c8]Oscar Moreira-Tamayo, José Pineda de Gyvez:
Preprocessing operators for image compression using cellular neural networks. ICNN 1996: 1500-1505 - 1995
- [c7]Apollo Q. Fong, Ajay Kanji, Edgar Sánchez-Sinencio, José Pineda de Gyvez:
A Universal Interface Between PC and Neural Networks Hardware. ISCAS 1995: 1169-1172 - [c6]Oscar Moreira-Tamayo, José Pineda de Gyvez:
Time Domain Analog Wavelet Transform in Real-Time. ISCAS 1995: 1640-1643 - 1994
- [c5]Chi-Chien Lee, José Pineda de Gyvez:
Single-Layer CNN Simulator. ISCAS 1994: 217-220 - [c4]John Willis, José Pineda de Gyvez:
Behavioral Testing of Cellular Neural Networks. ISCAS 1994: 229-232 - [c3]Chi-Chien Lee, José Pineda de Gyvez:
Time-Mulitplexing CNN Simulator. ISCAS 1994: 407-410 - [c2]Shyam S. Somayajula, Edgar Sánchez-Sinencio, José Pineda de Gyvez:
A power supply ramping and current measurement based technique for analog fault diagnosis. VTS 1994: 234-239 - 1993
- [b1]José Pineda de Gyvez:
Integrated circuit defect-sensitivity - theory and computational models. The Kluwer international series in engineering and computer science 208, Kluwer 1993, ISBN 978-0-7923-9306-1, pp. I-XXI, 1-167 - 1992
- [j2]José Pineda de Gyvez, Chennian Di:
IC defect sensitivity for footprint-type spot defects. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 11(5): 638-658 (1992)
1980 – 1989
- 1989
- [j1]José Pineda de Gyvez, Jochen A. G. Jess:
On the design and implementation of a wafer yield editor. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 8(8): 920-925 (1989) - [c1]José Pineda de Gyvez, Jochen A. G. Jess:
A layout defect-sensitivity extractor. ICCAD 1989: 538-541
Coauthor Index
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