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Poki Chen
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2020 – today
- 2024
- [j21]Joshua Adiel Wijaya
, Poki Chen
Area Efficient 0.009-mm2 28.1-ppm/°C 11.3-MHz ALL-MOS Relaxation Oscillator. IEEE Trans. Very Large Scale Integr. Syst. 32(10): 1900-1907 (2024) - 2023
- [j20]Ping-Hung Yin, Chih-Wen Lu
A 216 × 216 Global-Shutter CMOS Image Sensor With Embedded Analog Memory and Automatic Exposure Control for Under-Display Optical Fingerprint Sensing Applications. IEEE Trans. Circuits Syst. I Regul. Pap. 70(3): 1189-1201 (2023) - 2022
- [j19]Poki Chen
A 1-ps Bin Size 4.87-ps Resolution FPGA Time-to-Digital Converter Based on Phase Wrapping Sorting and Selection. IEEE Access 10: 126429-126439 (2022) - 2021
- [j18]Hsuan-Lun Kuo
An 18.39 fJ/Conversion-Step 1-MS/s 12-bit SAR ADC With Non-Binary Multiple-LSB-Redundant and Non-Integer-and-Split-Capacitor DAC. IEEE Access 9: 5651-5669 (2021) - [j17]Ping-Hung Yin, Chih-Wen Lu
A 368 × 184 Optical Under-Display Fingerprint Sensor Comprising Hybrid Arrays of Global and Rolling Shutter Pixels With Shared Pixel-Level ADCs. IEEE J. Solid State Circuits 56(3): 763-777 (2021) - [j16]Yu-Bang Chang, Chieh Tsai, Chang Hong Lin
Real-Time Semantic Segmentation with Dual Encoder and Self-Attention Mechanism for Autonomous Driving. Sensors 21(23): 8072 (2021) - [c12]Pei-Yi Lai Lee, Ya-Wen Yang, Sih-Han Li, Jian-Jhih Sun, Tzu Yi Hung, Chih-Wen Lu, Yen-Hsiang Fang, Wei-Hung Kuo, Li-Chun Huang, Guo-Dung John Su, Poki Chen:
A 1280 x 720 Micro-LED Display Driver with 10-Bit Current-Mode Pulse Width Modulation. A-SSCC 2021: 1-3 - 2020
- [j15]Nguyen My Qui
Design and Implementation of a 256-Bit RISC-V-Based Dynamically Scheduled Very Long Instruction Word on FPGA. IEEE Access 8: 172996-173007 (2020) - [j14]Poki Chen
High-Precision PLL Delay Matrix With Overclocking and Double Data Rate for Accurate FPGA Time-to-Digital Converters. IEEE Trans. Very Large Scale Integr. Syst. 28(4): 904-913 (2020) - [j13]Poki Chen
Low Flicker Dimmable Multichannel LED Driver With Matrix-Style DPWM and Precise Current Matching. IEEE Trans. Very Large Scale Integr. Syst. 28(11): 2233-2242 (2020)
2010 – 2019
- 2019
- [j12]Chih-Wen Lu
A 10-bit 1026-Channel Column Driver IC With Partially Segmented Piecewise Linear Digital-to-Analog Converters for UHD TFT-LCDs With One Billion Color Display. IEEE J. Solid State Circuits 54(10): 2703-2716 (2019) - [j11]Massimo Alioto, Magdy S. Abadir, Tughrul Arslan, Chirn Chye Boon, Andreas Burg
Editorial TVLSI Positioning - Continuing and Accelerating an Upward Trajectory. IEEE Trans. Very Large Scale Integr. Syst. 27(2): 253-280 (2019) - [c11]Yousuke Miyake
On-Chip Test Clock Validation Using A Time-to-Digital Converter in FPGAs. ITC-Asia 2019: 157-162 - 2018
- [j10]Tao-Chun Yu, Shao-Yun Fang
Device Array Layout Synthesis With Nonlinear Gradient Compensation for a High-Accuracy Current-Steering DAC. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37(4): 717-728 (2018) - 2017
- [j9]Krishnendu Chakrabarty
Editorial. IEEE Trans. Very Large Scale Integr. Syst. 25(1): 1-20 (2017) - [j8]Poki Chen
A 2.5-ps Bin Size and 6.7-ps Resolution FPGA Time-to-Digital Converter Based on Delay Wrapping and Averaging. IEEE Trans. Very Large Scale Integr. Syst. 25(1): 114-124 (2017) - 2015
- [c10]Poki Chen, Yi-Jiang Hu, Jian-Cheng Liou, Bo-Chang Ren:
A 486k S/s CMOS time-domain smart temperature sensor with -0.85°C/0.78°C voltage-calibrated error. ISCAS 2015: 2109-2112 - [c9]Poki Chen, Hsien-Chih Liu, Ya-Wen Yang, Ya-Ying Li, Fajar Budiman:
A multi-channel high precision current matching LED Driver for intelligent dimming. ISPACS 2015: 174-177 - 2011
- [j7]Poki Chen, Shou-Chih Chen, You-Sheng Shen, You-Jyun Peng:
All-Digital Time-Domain Smart Temperature Sensor With an Inter-Batch Inaccuracy of -0.7~°C - +0.6~°C After One-Point Calibration. IEEE Trans. Circuits Syst. I Regul. Pap. 58-I(5): 913-920 (2011) - 2010
- [j6]Poki Chen, Chun-Chi Chen, Yu-Han Peng, Kai-Ming Wang, Yu-Shin Wang:
A Time-Domain SAR Smart Temperature Sensor With Curvature Compensation and a 3σ Inaccuracy of -0.4°C ∼ +0.6°C Over a 0°C to 90°C Range. IEEE J. Solid State Circuits 45(3): 600-609 (2010) - [j5]Poki Chen, Po-Yu Chen, Juan-Shan Lai, Yi-Jin Chen:
FPGA Vernier Digital-to-Time Converter With 1.58 ps Resolution and 59.3 Minutes Operation Range. IEEE Trans. Circuits Syst. I Regul. Pap. 57-I(6): 1134-1142 (2010)
2000 – 2009
- 2009
- [j4]Poki Chen, Ting-Chun Liu:
Switching Schemes for Reducing Capacitor Mismatch Sensitivity of Quasi-Passive Cyclic DAC. IEEE Trans. Circuits Syst. II Express Briefs 56-II(1): 26-30 (2009) - 2008
- [c8]Poki Chen, Juan-Shan Lai, Po-Yu Chen:
A FPGA vernier digital-to-time converter with 3.56ps resolution and -0.23∼+0.2LSB inaccuracy. CICC 2008: 209-212 - [c7]Poki Chen, Kai-Ming Wang, Yu-Han Peng, Yu-Shin Wang, Chun-Chi Chen:
A time-domain SAR smart temperature sensor with -0.25∼+0.35°C inaccuracy for on-chip monitoring. ESSCIRC 2008: 70-73 - 2007
- [j3]Poki Chen, Mon-Chau Shie, Zhi-Yuan Zheng, Zi-Fan Zheng, Chun-Yan Chu:
A Fully Digital Time-Domain Smart Temperature Sensor Realized With 140 FPGA Logic Elements. IEEE Trans. Circuits Syst. I Regul. Pap. 54-I(12): 2661-2668 (2007) - 2006
- [c6]Poki Chen, Chun-Chi Chen, Tuo-Kuang Chen, Shi-Wei Chen:
A Time Domain Mixed-Mode Temperature Sensor with Digital Set-Point Programming. CICC 2006: 821-824 - 2005
- [j2]Poki Chen, Chun-Chi Chen, Chin-Chung Tsai
A time-to-digital-converter-based CMOS smart temperature sensor. IEEE J. Solid State Circuits 40(8): 1642-1648 (2005) - [c5]Poki Chen, Jia-Chi Zheng, Chun-Chi Chen:
A monolithic vernier-based time-to-digital converter with dual PLLs for self-calibration. CICC 2005: 321-324 - [c4]Chun-Chi Chen, Wen-Fu Lu, Chin-Chung Tsai
A time-to-digital-converter-based CMOS smart temperature sensor. ISCAS (1) 2005: 560-563 - 2004
- [c3]Chorng-Sii Hwang, Poki Chen, Hen-Wai Tsao:
A wide-range and fast-locking clock synthesizer IP based on delay-locked loop. ISCAS (1) 2004: 785-788 - 2003
- [c2]Chorng-Sii Hwang, Poki Chen, Hen-Wai Tsao:
A high-resolution and fast-conversion time-to-digital converter. ISCAS (1) 2003: 37-40
1990 – 1999
- 1999
- [c1]Poki Chen, Shen-Iuan Liu:
A cyclic CMOS time-to-digital converter with deep sub-nanosecond resolution. CICC 1999: 605-608 - 1991
- [j1]Poki Chen, Jin-Fu Chang:
An improved transmission protocol for two interfering queues in packet radio networks. IEEE Trans. Commun. 39(3): 353-355 (1991)
Coauthor Index
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