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25th FCCM 2017: Napa, CA, USA
- 25th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, FCCM 2017, Napa, CA, USA, April 30 - May 2, 2017. IEEE Computer Society 2017, ISBN 978-1-5386-4037-1
Session 1: Applications (Big Data)
- Susumu Mashimo, Thiem Van Chu, Kenji Kise:
High-Performance Hardware Merge Sorter. 1-8 - Shuanglong Liu, Christos-Savvas Bouganis
:
Communication-Aware MCMC Method for Big Data Applications on FPGAs. 9-16 - Sang Woo Jun
Terabyte Sort on FPGA-Accelerated Flash Storage. 17-24
Poster Session P1
- Le Tu, Yuelai Yuan, Kan Huang, Xiaoqiang Zhang, Zixin Wang, Dihu Chen:
Improved Synthesis of Compressor Trees on FPGAs in High-Level Synthesis. 25 - David Ojika, Piotr Majcher, Wojciech Neubauer, Suchit Subhaschandra, Darin Acosta:
SWiF: A Simplified Workload-Centric Framework for FPGA-Based Computing. 26 - Minghua Shen, Guojie Luo:
Megrez: Parallelizing FPGA Routing with Strictly-Ordered Partitioning. 27 - Sicheng Li, Wei Wen, Yu Wang, Song Han, Yiran Chen, Hai Li
An FPGA Design Framework for CNN Sparsification and Acceleration. 28 - Qiang Liu, HanJing Qian:
FPGA Delay Model Considering Logic-Level and Transistor-Level Parameters. 29 - Nguyen T. H. Nguyen, Ediz Cetin
Scheduling Considerations for Voter Checking in TMR-MER Systems. 30 - Jianxin Guo, Shouyi Yin, Peng Ouyang, Leibo Liu
Bit-Width Based Resource Partitioning for CNN Acceleration on FPGA. 31
Session 2: Overlays
- Nachiket Kapre:
On Bit-Serial NoCs for FPGAs. 32-39 - Nachiket Kapre:
Implementing FPGA Overlay NoCs Using the Xilinx UltraScale Memory Cascades. 40-47 - Ashutosh Dhar, Deming Chen:
Efficient GPGPU Computing with Cross-Core Resource Sharing and Core Reconfiguration. 48-55
Session 3: Applications (Physics and Biology)
- Emmanouil Kousanakis, Apostolos Dollas, Euripides Sotiriades, Ioannis Papaefstathiou
An Architecture for the Acceleration of a Hybrid Leaky Integrate and Fire SNN on the Convey HC-2ex FPGA-Based Processor. 56-63 - Edward Bartz, Jorge Chaves, Yuri Gershtein, Eva Halkiadakis, Michael D. Hildreth, Savvas Kyriacou, Kevin Lannon
FPGA-Based Real-Time Charged Particle Trajectory Reconstruction at the Large Hadron Collider. 64-71 - Qingqing Xiong, Martin C. Herbordt:
Bonded Force Computations on FPGAs. 72-75 - Abedalmuhdi Almomany
Efficient Particle-Grid Space Interpolation of an FPGA-Accelerated Particle-in-Cell Plasma Simulation. 76-79
Poster Session P2
- Yohann Uguen, Florent de Dinechin, Steven Derrien:
A High-Level Synthesis Approach Optimizing Accumulations in Floating-Point Programs Using Custom Formats and Operators. 80 - Reza Nakhjavani, Jianwen Zhu:
A Case for Common-Case: On FPGA Acceleration of Erasure Coding. 81 - Soroosh Khoram, Jialiang Zhang, Maxwell Strange, Jing Li
Accelerating Large-Scale Graph Analytics with FPGA and HMC. 82 - Baptiste Roux, Matthieu Gautier, Olivier Sentieys, Jean-Philippe Delahaye:
Fast and Energy-Driven Design Space Exploration for Heterogeneous Architectures. 83 - Sam M. H. Ho, C.-H. Dominic Hung, Ho-Cheung Ng, Maolin Wang, Hayden Kwok-Hay So
A Parameterizable Activation Function Generator for FPGA-Based Neural Network Applications. 84
Session 4: Applications (Machine Learning)
- Mohammad Samragh, Mohammad Ghasemzadeh, Farinaz Koushanfar
Customizing Neural Networks for Efficient FPGA Implementation. 85-92 - Yongming Shen, Michael Ferdman, Peter A. Milder
Escher: A CNN Accelerator with Flexible Buffering to Minimize Off-Chip Transfer. 93-100 - Liqiang Lu, Yun Liang, Qingcheng Xiao, Shengen Yan:
Evaluating Fast Algorithms for Convolutional Neural Networks on FPGAs. 101-108
Session 5: High Level Synthesis
- Shane T. Fleming, David B. Thomas:
Using Runahead Execution to Hide Memory Latency in High Level Synthesis. 109-116 - Naveen Kumar Dumpala, Shivukumar B. Patil, Daniel E. Holcomb, Russell Tessier:
Energy Efficient Loop Unrolling for Low-Cost FPGAs. 117-120 - Andrew G. Schmidt, Gabriel Weisz, Matthew French:
Evaluating Rapid Application Development with Python for Heterogeneous Processor-Based FPGAs. 121-124 - Young Kyu Choi
HLScope: High-Level Performance Debugging for FPGA Designs. 125-128 - Ganghee Lee, Dimitris Agiakatsikas
TLegUp: A TMR Code Generation Tool for SRAM-Based FPGA Applications Using HLS. 129-132
Poster Session P3
- Jong Hun Han, Neelakandan Manihatty Bojan, Andrew W. Moore:
Exploration of FPGA-Based Packet Switches for Rack-Scale Computers on a Board. 133 - Lana Josipovic
An Out-of-Order Load-Store Queue for Spatial Computing. 134 - Philip Colangelo, Randy Huang, Enno Lübbers, Martin Margala, Kevin Nealis:
Fine-Grained Acceleration of Binary Neural Networks Using Intel® Xeon® Processor with Integrated FPGA. 135
Session 6: Test and Debug
- Jeffrey Goeders:
Enabling Long Debug Traces of HLS Circuits Using Bandwidth-Limited Off-Chip Storage Devices. 136-143 - John Mawer, Oscar Palomar
The Potential of Dynamic Binary Modification and CPU-FPGA SoCs for Simulation. 144-151
Session 7: Applications (Machine Learning 2)
- Yijin Guan, Hao Liang, Ningyi Xu, Wenqiang Wang, Shaoshuai Shi, Xi Chen, Guangyu Sun, Wei Zhang, Jason Cong:
FP-DNN: An Automated Framework for Mapping Deep Neural Networks onto FPGAs with RTL-HLS Hybrid Templates. 152-159 - Kaan Kara, Dan Alistarh, Gustavo Alonso, Onur Mutlu, Ce Zhang:
FPGA-Accelerated Dense Linear Machine Learning: A Precision-Convergence Trade-Off. 160-167 - Ahmed M. Abdelsalam, J. M. Pierre Langlois, Farida Cheriet:
A Configurable FPGA Implementation of the Tanh Function Using DCT Interpolation. 168-171
Session 8: CAD Tools
- Chin Hau Hoo, Akash Kumar:
ParaDiMe: A Distributed Memory FPGA Router Based on Speculative Parallelism and Path Encoding. 172-179 - Jack Wadden, Samira Manabi Khan, Kevin Skadron
Automata-to-Routing: An Open-Source Toolchain for Design-Space Exploration of Spatial Automata Processing Architectures. 180-187 - Adewale Adetomi, Godwin Enemali
Relocating Encrypted Partial Bitstreams by Advance Task Address Loading. 188-191
Poster Session P4
- Hoang Gia Vu
CPRring: A Structure-Aware Ring-Based Checkpointing Architecture for FPGA Computing. 192 - Dimitris Theodoropoulos, Nikolaos Alachiotis, Dionisios N. Pnevmatikatos
Multi-FPGA Evaluation Platform for Disaggregated Computing. 193 - Fubing Mao, Wei Zhang, Bingsheng He
Dynamic Module Partitioning for Library Based Placement on Heterogeneous FPGAs. 194 - Qian Wu, Yongxin Zhu, Xu Wang, Mengjun Li, Junjie Hou, Ali Masoumi:
Exploring High Efficiency Hardware Accelerator for the Key Algorithm of Square Kilometer Array Telescope Data Processing. 195 - Raghid Morcel, Haitham Akkary, Hazem M. Hajj, Mazen A. R. Saghir, Anil S. Keshavamurthy, Rahul Khanna, Hassan Artail:
Minimalist Design for Accelerating Convolutional Neural Networks for Low-End FPGA Platforms. 196 - Ian J. Barge, Cristinel Ababei:
A Network-on-Chip Based H.264 Video Decoder Prototype Implemented on FPGAs. 197 - Festus Hategekimana, Christophe Bobda:
Applying the Flask Security Architecture to Secure SoC Design. 198 - Ali Jafari, Maysam Ghovanloo, Tinoosh Mohsenin:
A Real-Time Embedded FPGA Processor for a Stand-Alone Dual-Mode Assistive Device. 199 - Taylor J. L. Whitaker, Christophe Bobda:
CAPSL: A Tool for Automatic Generation of Hardware Sandboxes for IP Security. 200 - Morteza Hosseini, Rashidul Islam, Amey M. Kulkarni, Tinoosh Mohsenin:
A Scalable FPGA-Based Accelerator for High-Throughput MCMC Algorithms. 201 - Youngsoo Kim, Hossein Shahdoost, Shrikant Jadhav
Improving the Accuracy of Arctan for Face Detection. 202
Session 9: Applications (Big Data 2)
- Nathaniel McVicar, Chih-Ching Lin, Scott Hauck:
K-Mer Counting Using Bloom Filters with an FPGA-Attached HMC. 203-210 - Muhsen Owaida, David Sidler, Kaan Kara, Gustavo Alonso:
Centaur: A Framework for Hybrid CPU-FPGA Databases. 211-218 - Xuzhi Zhang, Xiaozhe Shao, George Provelengios, Naveen Kumar Dumpala, Lixin Gao, Russell Tessier:
Scalable Network Function Virtualization for Heterogeneous Middleboxes. 219-226 - Haohuan Fu, Conghui He, Wayne Luk, Weijia Li, Guangwen Yang:
A Nanosecond-Level Hybrid Table Design for Financial Market Data Generators. 227-234
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