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Mazen A. R. Saghir
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2020 – today
- 2023
- [c28]Yasmine Abu Adla, Mazen A. R. Saghir, Mariette Awad
:
Real-Time Arabic Digit Spotting with TinyML-Optimized CNNs on Edge Devices. AIAI (1) 2023: 527-538 - [c27]Walaa Amer, Mariam Rakka, Rachid Karami, Minjun Seo, Mazen A. R. Saghir, Rouwaida Kanj, Fadi J. Kurdahi:
Hardware Implementation and Evaluation of an Information Processing Factory. VLSI-SoC 2023: 1-6 - 2021
- [i1]Imad Al Assir
Arrow: A RISC-V Vector Accelerator for Machine Learning Inference. CoRR abs/2107.07169 (2021) - 2020
- [c26]Alaa Maarouf, Nour El Droubi, Raghid Morcel, Hazem M. Hajj, Mazen A. R. Saghir, Haitham Akkary:
Optimized Distribution of an Accelerated Convolutional Neural Network across Multiple FPGAs. FCCM 2020: 235
2010 – 2019
- 2019
- [j12]Hassan Artail
Speedy Cloud: Cloud Computing with Support for Hardware Acceleration Services. IEEE Trans. Cloud Comput. 7(3): 850-865 (2019) - [j11]Raghid Morcel
FeatherNet: An Accelerated Convolutional Neural Network Design for Resource-constrained FPGAs. ACM Trans. Reconfigurable Technol. Syst. 12(2): 6:1-6:27 (2019) - 2018
- [j10]Mohammed S. BenSaleh, Yaman Sharaf-Dabbagh, Hazem M. Hajj, Mazen A. R. Saghir, Haitham Akkary, Hassan Artail, Abdulfattah Mohammad Obeid, Syed Manzoor Qasim
Optimal Task Scheduling for Distributed Cluster With Active Storage Devices and Accelerated Nodes. IEEE Access 6: 48195-48209 (2018) - [j9]Mageda Sharafeddine, Hmayag Partamian, Mariette Awad, Mazen A. R. Saghir, Haitham Akkary, Hassan Artail, Hazem M. Hajj, Mohammed Baydoun:
Towards distributed acceleration of image processing applications using reconfigurable active SSD clusters: a case study of seismic data analysis. Int. J. High Perform. Comput. Netw. 11(4): 261-278 (2018) - [c25]Mazen Ezzeddine
RESTful Hardware Microservices Using Reconfigurable Networked Accelerators in Cloud and Edge Datacenters. CloudNet 2018: 1-4 - [c24]Anthony Mattar El Raachini, Hussein Alawieh, Adam Issa, Zainab Swaidan, Rouwaida Kanj, Ali Chehab
Double error cellular automata-based error correction with skip-mode compact syndrome coding for resilient PUF design. ISQED 2018: 413-418 - [e1]Smaïl Niar, Mazen A. R. Saghir:
13th International Symposium on Reconfigurable Communication-centric Systems-on-Chip, ReCoSoC 2018, Lille, France, July 9-11, 2018. IEEE 2018, ISBN 978-1-5386-7957-9 [contents] - 2017
- [j8]Khaleel W. Mershad
A Study of the Performance of a Cloud Datacenter Server. IEEE Trans. Cloud Comput. 5(4): 590-603 (2017) - [c23]Raghid Morcel, Haitham Akkary, Hazem M. Hajj, Mazen A. R. Saghir, Anil S. Keshavamurthy, Rahul Khanna, Hassan Artail:
Minimalist Design for Accelerating Convolutional Neural Networks for Low-End FPGA Platforms. FCCM 2017: 196 - 2016
- [j7]Hussein Sharafeddin, Mazen A. R. Saghir, Haitham Akkary, Hassan Artail, Hazem M. Hajj:
On the effectiveness of accelerating MapReduce functions using the Xilinx Vivado HLS tool. Int. J. High Perform. Syst. Archit. 6(1): 1-12 (2016) - [j6]Khaleel W. Mershad
A mathematical model to analyze the utilization of a cloud datacenter middleware. J. Netw. Comput. Appl. 59: 399-415 (2016) - [c22]Ihsen Alouani, Smaïl Niar, Yassin El Hillali, Mazen A. R. Saghir, Fadi J. Kurdahi, Menhaj Atika:
Auto-tuning Fault Tolerance Technique for DSP-Based Circuits in Transportation Systems. RES4ANT@DATE 2016: 33-37 - [c21]Maya H. Safieddine, Fadi A. Zaraket
Automated FPGA implementations of BIP designs. SIES 2016: 165-170 - 2014
- [j5]Abdul Rahman Kaitoua, Hazem M. Hajj, Mazen A. R. Saghir, Hassan Artail, Haitham Akkary, Mariette Awad
Hadoop Extensions for Distributed Computing on Reconfigurable Active SSD Clusters. ACM Trans. Archit. Code Optim. 11(2): 22:1-22:26 (2014) - [c20]Ihsen Alouani
ARABICA: A Reconfigurable Arithmetic Block for ISA Customization. ARC 2014: 248-253 - [c19]Mageda Sharafeddine
On the efficiency of automatically generated accelerators for reconfigurable active SSDs. ICM 2014: 124-127 - 2013
- [j4]Abbes Amira, Mazen A. R. Saghir, Naeem Ramzan
A Reconfigurable Wireless Environment for ECG Monitoring and Encryption. Int. J. Embed. Real Time Commun. Syst. 4(3): 72-87 (2013) - [j3]Ahmed M. Eltawil
A survey of cross-layer power-reliability tradeoffs in multi and many core systems-on-chip. Microprocess. Microsystems 37(8-A): 760-771 (2013) - [c18]Mohamad Jomaa, Khaleel W. Mershad
A Mediation Layer for Connecting Data-Intensive Applications to Reconfigurable Data Nodes. ICCCN 2013: 1-9 - [c17]Khaleel Mershad
Cloud providers collaboration for a higher service level in cloud computing. ICCIT 2013: 109-114 - [c16]Ali Ali, Mazen A. R. Saghir, Haitham Akkary, Hassan Artail, Hazem M. Hajj, Mariette Awad
RASSD: A dynamically reconfigurable active storage device for energy efficient data analytics. ICEAC 2013: 81-86 - [c15]Khaleel W. Mershad
A Framework for Multi-cloud Cooperation with Hardware Reconfiguration Support. SERVICES 2013: 52-59 - 2012
- [c14]Ali Ali, Mohamad Jomaa, Bashar Romanous, Mageda Sharafeddine
An operating system for a Reconfigurable Active SSD processing node. ICT 2012: 1-6 - 2011
- [c13]Noor Abbani, Ali Ali, Doa'A Al Otoom, Mohamad Jomaa, Mageda Sharafeddine
A Distributed Reconfigurable Active SSD Platform for Data Intensive Applications. HPCC 2011: 25-34 - [c12]Amir Hossein Gholamipour, Ali Gorcin
Reconfigurable filter implementation of a matched-filter based spectrum sensor for Cognitive Radio systems. ISCAS 2011: 2457-2460 - [c11]Naim Harb, Smaïl Niar, Mazen A. R. Saghir, Yassin Elhillali, Rabie Ben Atitallah:
Dynamically reconfigurable architecture for a driver assistant system. SASP 2011: 62-65 - 2010
- [c10]Amir Hossein Gholamipour, Fadi J. Kurdahi
Exploiting Architectural Similarities and Mode Sequencing in Joint Cost Optimization of Multi-mode FIR Filters. FPL 2010: 175-178 - [c9]Amir Hossein Gholamipour, Fadi J. Kurdahi
Placement-aware partial reconfiguration for a class of FIR-like structures. ICT 2010: 965-972
2000 – 2009
- 2009
- [j2]Jehangir Khan, Smaïl Niar, Mazen A. R. Saghir, Yassin Elhillali, Atika Rivenq-Menhaj:
Trade-Off Exploration for Target Tracking Application in a Customized Multiprocessor Architecture. EURASIP J. Embed. Syst. 2009 (2009) - [j1]Naim Harb, Smaïl Niar, Jehangir Khan, Mazen A. R. Saghir:
A reconfigurable platform architecture for an automotive multiple-target tracking system. SIGBED Rev. 6(3): 13 (2009) - [c8]Jehangir Khan, Smaïl Niar, Mazen A. R. Saghir, Yassin Elhillali, Atika Rivenq:
Driver assistance system design and its optimization for FPGA based MPSoC. SASP 2009: 62-65 - 2007
- [c7]Mazen A. R. Saghir, Rawan Naous:
A Configurable Multi-ported Register File Architecture for Soft Processor Cores. ARC 2007: 14-25 - [c6]Roger Moussali, Nabil Ghanem, Mazen A. R. Saghir:
Supporting multithreading in configurable soft processor cores. CASES 2007: 155-159 - [c5]Roger Moussali, Nabil Ghanem, Mazen A. R. Saghir:
Microarchitectural Enhancements for Configurable Multi-Threaded Soft Processors. FPL 2007: 782-785 - [c4]Mazen A. R. Saghir, Mohamad El-Majzoub, Patrick Akl:
Customizing the Datapath and ISA of Soft VLIW Processors. HiPEAC 2007: 276-290 - 2006
- [c3]Mazen A. R. Saghir, Mohamad El-Majzoub, Patrick Akl:
Datapath and ISA Customization for Soft VLIW Processors. ReConFig 2006: 280-289
1990 – 1999
- 1996
- [c2]Mazen A. R. Saghir, Paul Chow, Corinna G. Lee:
Exploiting Dual Data-Memory Banks in Digital Signal Processors. ASPLOS 1996: 234-243 - 1994
- [c1]Mazen A. R. Saghir, Paul Chow, Corinna G. Lee:
Application-driven design of DSP architectures and compilers. ICASSP (2) 1994: 437-440
Coauthor Index
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