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Hayden Kwok-Hay So
Hayden K. H. So
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- affiliation: University of Hong Kong
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2020 – today
- 2024
- [j30]Jiajun Zhou, Jiajun Wu, Yizhao Gao, Yuhao Ding, Chaofan Tao, Boyu Li, Fengbin Tu, Kwang-Ting Cheng, Hayden Kwok-Hay So, Ngai Wong:
DyBit: Dynamic Bit-Precision Numbers for Efficient Quantized Neural Network Inference. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 43(5): 1613-1617 (2024) - [c70]Baoheng Zhang, Yizhao Gao, Jingyuan Li, Hayden Kwok-Hay So:
Co-designing a Sub-millisecond Latency Event-based Eye Tracking System with Submanifold Sparse CNN. CVPR Workshops 2024: 5771-5779 - [c69]Zuowen Wang, Chang Gao, Zongwei Wu, Marcos V. Conde, Radu Timofte, Shih-Chii Liu, Qinyu Chen, Zhengjun Zha, Wei Zhai, Han Han, Bohao Liao, Yuliang Wu, Zengyu Wan, Zhong Wang, Yang Cao, Ganchao Tan, Jinze Chen, Yan Ru Pei, Sasskia Brüers, Sébastien M. Crouzet, Douglas McLelland, Olivier Coenen, Baoheng Zhang, Yizhao Gao, Jingyuan Li, Hayden Kwok-Hay So, Philippe Bich, Chiara Boretti, Luciano Prono, Mircea Lica, David Dinucu-Jianu, Catalin Grîu, Xiaopeng Lin, Hongwei Ren, Bojun Cheng, Xinan Zhang, Valentin Vial, Anthony Yezzi, James Tsai:
Event-Based Eye Tracking. AIS 2024 Challenge Survey. CVPR Workshops 2024: 5810-5825 - [c68]Yizhao Gao
, Baoheng Zhang
A Composable Dynamic Sparse Dataflow Architecture for Efficient Event-based Vision Processing on FPGA. FPGA 2024: 246-257 - [c67]Hayden Kwok-Hay So:
RAW 2024 Invited Talk-8: Practical Reconfigurable Computing for Next-Generation Edge Applications. IPDPS (Workshops) 2024: 90 - [c66]Jiajun Wu, Mo Song, Jingmin Zhao, Hayden Kwok-Hay So:
A Case for Low Bitwidth Floating Point Arithmetic on FPGA for Transformer Based DNN Inference. IPDPS (Workshops) 2024: 178-185 - [c65]Maolin Wang, Ian McInerney, Bartolomeo Stellato, Fengbin Tu, Stephen P. Boyd, Hayden Kwok-Hay So, Kwang-Ting Cheng:
Multi-Issue Butterfly Architecture for Sparse Convex Quadratic Programming. MICRO 2024: 1574-1587 - [i20]Yizhao Gao, Baoheng Zhang, Yuhao Ding, Hayden Kwok-Hay So:
A Composable Dynamic Sparse Dataflow Architecture for Efficient Event-based Vision Processing on FPGA. CoRR abs/2401.05626 (2024) - [i19]Zuowen Wang, Chang Gao, Zongwei Wu, Marcos V. Conde, Radu Timofte, Shih-Chii Liu, Qinyu Chen
Event-Based Eye Tracking. AIS 2024 Challenge Survey. CoRR abs/2404.11770 (2024) - [i18]Baoheng Zhang, Yizhao Gao, Jingyuan Li, Hayden Kwok-Hay So:
Co-designing a Sub-millisecond Latency Event-based Eye Tracking System with Submanifold Sparse CNN. CoRR abs/2404.14279 (2024) - [i17]Yizhao Gao, Zhichen Zeng, Dayou Du, Shijie Cao, Hayden Kwok-Hay So, Ting Cao, Fan Yang, Mao Yang:
SeerAttention: Learning Intrinsic Sparse Attention in Your LLMs. CoRR abs/2410.13276 (2024) - 2023
- [j29]Yizhao Gao
A Reconfigurable Architecture for Real-time Event-based Multi-Object Tracking. ACM Trans. Reconfigurable Technol. Syst. 16(4): 58:1-58:26 (2023) - [c64]Yizhao Gao, Baoheng Zhang, Xiaojuan Qi, Hayden Kwok-Hay So
DPACS: Hardware Accelerated Dynamic Neural Network Pruning through Algorithm-Architecture Co-design. ASPLOS (2) 2023: 237-251 - [c63]Yuhao Ding, Jiajun Wu, Yizhao Gao, Maolin Wang, Hayden Kwok-Hay So
Model-Platform Optimized Deep Neural Network Accelerator Generation through Mixed-Integer Geometric Programming. FCCM 2023: 83-93 - [c62]Jiajun Wu, Jiajun Zhou, Yizhao Gao, Yuhao Ding, Ngai Wong, Hayden Kwok-Hay So:
MSD: Mixing Signed Digit Representations for Hardware-efficient DNN Acceleration on FPGA with Heterogeneous Resources. FCCM 2023: 94-104 - [c61]Mo Song, Jiajun Wu, Yuhao Ding, Hayden Kwok-Hay So:
SqueezeBlock: A Transparent Weight Compression Scheme for Deep Neural Networks. ICFPT 2023: 238-243 - [c60]Zhenyu Wu
Towards Asynchronously Triggered Spiking Neural Network on FPGA for Event-based Vision. ICFPT 2023: 292-293 - [c59]Maolin Wang
RSQP: Problem-specific Architectural Customization for Accelerated Convex Quadratic Optimization. ISCA 2023: 73:1-73:12 - [i16]Jiajun Zhou
DyBit: Dynamic Bit-Precision Numbers for Efficient Quantized Neural Network Inference. CoRR abs/2302.12510 (2023) - [i15]Song Wang, Zhu Wang, Can Li, Xiaojuan Qi, Hayden Kwok-Hay So:
SpikeMOT: Event-based Multi-Object Tracking with Sparse Motion Features. CoRR abs/2309.16987 (2023) - [i14]Shaocong Wang, Yizhao Gao, Yi Li, Woyu Zhang, Yifei Yu, Bo Wang, Ning Lin, Hegan Chen, Yue Zhang, Yang Jiang, Dingchen Wang, Jia Chen, Peng Dai, Hao Jiang, Peng Lin, Xumeng Zhang, Xiaojuan Qi, Xiaoxin Xu, Hayden K. H. So, Zhongrui Wang, Dashan Shang, Qi Liu, Kwang-Ting Cheng, Ming Liu:
Random resistive memory-based deep extreme point learning machine for unified visual processing. CoRR abs/2312.09262 (2023) - 2022
- [j28]Maolin Wang
Low-Latency In Situ Image Analytics With FPGA-Based Quantized Convolutional Neural Network. IEEE Trans. Neural Networks Learn. Syst. 33(7): 2853-2866 (2022) - [j27]Maolin Wang
NITI: Training Integer Neural Networks Using Integer-Only Arithmetic. IEEE Trans. Parallel Distributed Syst. 33(11): 3249-3261 (2022) - [c58]Yizhao Gao
REMOT: A Hardware-Software Architecture for Attention-Guided Multi-Object Tracking with Dynamic Vision Sensors on FPGAs. FPGA 2022: 158-168 - 2021
- [j26]Nan Meng
High-Dimensional Dense Residual Convolutional Neural Network for Light Field Reconstruction. IEEE Trans. Pattern Anal. Mach. Intell. 43(3): 873-886 (2021) - [c57]Zhen Dong, Yizhao Gao
HAO: Hardware-aware Neural Architecture Optimization for Efficient Inference. FCCM 2021: 50-59 - [c56]Sung-En Chang, Yanyu Li, Mengshu Sun
Mix and Match: A Novel FPGA-Centric Deep Neural Network Quantization Framework. HPCA 2021: 208-220 - [i13]Zhen Dong, Yizhao Gao, Qijing Huang, John Wawrzynek, Hayden K. H. So, Kurt Keutzer:
HAO: Hardware-aware neural Architecture Optimization for Efficient Inference. CoRR abs/2104.12766 (2021) - [i12]Jie Ran, Rui Lin, Hayden K. H. So, Graziano Chesi, Ngai Wong:
Exploiting Elasticity in Tensor Ranks for Compressing Neural Networks. CoRR abs/2105.04218 (2021) - 2020
- [j25]Shobana V. Stassen, Dickson M. D. Siu
PARC: ultrafast and accurate clustering of phenotypic data of millions of single cells. Bioinform. 36(9): 2778-2786 (2020) - [c55]Runbin Shi, Yuhao Ding, Xuechao Wei, He Li, Hang Liu, Hayden Kwok-Hay So
FTDL: A Tailored FPGA-Overlay for Deep Learning with High Scalability. DAC 2020: 1-6 - [c54]Runbin Shi, Yuhao Ding, Xuechao Wei, Hang Liu, Hayden Kwok-Hay So
FTDL: An FPGA-tailored Architecture for Deep Learning Systems. FPGA 2020: 320 - [c53]Junjie Liu, Zhe Xu, Runbin Shi, Ray C. C. Cheung, Hayden Kwok-Hay So:
Dynamic Sparse Training: Find Efficient Sparse Network From Scratch With Trainable Masked Layers. ICLR 2020 - [c52]Jie Ran, Rui Lin, Hayden K. H. So
Exploiting Elasticity in Tensor Ranks for Compressing Neural Networks. ICPR 2020: 9866-9873 - [c51]Runbin Shi, Peiyan Dong, Tong Geng, Yuhao Ding, Xiaolong Ma, Hayden Kwok-Hay So
CSB-RNN: a faster-than-realtime RNN acceleration framework with compressed structured blocks. ICS 2020: 24:1-24:12 - [c50]Cyrus Wing-Hei Chan, Philip H. W. Leong, Hayden Kwok-Hay So
Vision Guided Crop Detection in Field Robots using FPGA-Based Reconfigurable Computers. ISCAS 2020: 1-5 - [e2]Fernando Rincón
Applied Reconfigurable Computing. Architectures, Tools, and Applications - 16th International Symposium, ARC 2020, Toledo, Spain, April 1-3, 2020, Proceedings [postponed]. Lecture Notes in Computer Science 12083, Springer 2020, ISBN 978-3-030-44533-1 [contents] - [i11]Runbin Shi, Peiyan Dong, Tong Geng, Yuhao Ding, Xiaolong Ma, Hayden Kwok-Hay So, Martin C. Herbordt, Ang Li, Yanzhi Wang:
CSB-RNN: A Faster-than-Realtime RNN Acceleration Framework with Compressed Structured Blocks. CoRR abs/2005.05758 (2020) - [i10]Junjie Liu, Zhe Xu, Runbin Shi, Ray C. C. Cheung, Hayden Kwok-Hay So:
Dynamic Sparse Training: Find Efficient Sparse Network From Scratch With Trainable Masked Layers. CoRR abs/2005.06870 (2020) - [i9]Maolin Wang, Seyedramin Rasoulinezhad, Philip H. W. Leong, Hayden Kwok-Hay So:
NITI: Training Integer Neural Networks Using Integer-only Arithmetic. CoRR abs/2009.13108 (2020) - [i8]Sung-En Chang, Yanyu Li, Mengshu Sun, Runbin Shi, Hayden Kwok-Hay So, Xuehai Qian, Yanzhi Wang, Xue Lin:
Mix and Match: A Novel FPGA-Centric Deep Neural Network Quantization Framework. CoRR abs/2012.04240 (2020)
2010 – 2019
- 2019
- [j24]Nan Meng
Computational Light Field Generation Using Deep Nonparametric Bayesian Learning. IEEE Access 7: 24990-25000 (2019) - [j23]Manish Kumar Jaiswal
PACoGen: A Hardware Posit Arithmetic Core Generator. IEEE Access 7: 74586-74601 (2019) - [j22]Manish Kumar Jaiswal
Design of quadruple precision multiplier architectures with SIMD single and double precision support. Integr. 65: 163-174 (2019) - [j21]Runbin Shi
High-Throughput Line Buffer Microarchitecture for Arbitrary Sized Streaming Image Processing. J. Imaging 5(3): 34 (2019) - [j20]Runbin Shi
A Real-Time Coprime Line Scan Super-Resolution System for Ultra-Fast Microscopy. IEEE Trans. Biomed. Circuits Syst. 13(4): 781-792 (2019) - [j19]Zhenbo Ren
Fringe Pattern Improvement and Super-Resolution Using Deep Learning in Digital Holography. IEEE Trans. Ind. Informatics 15(11): 6179-6186 (2019) - [j18]Nan Meng
Large-Scale Multi-Class Image-Based Cell Classification With Deep Learning. IEEE J. Biomed. Health Informatics 23(5): 2091-2098 (2019) - [j17]Nina Engelhardt, Hayden Kwok-Hay So
GraVF-M: Graph Processing System Generation for Multi-FPGA Platforms. ACM Trans. Reconfigurable Technol. Syst. 12(4): 21:1-21:28 (2019) - [c49]Runbin Shi, Junjie Liu, Hayden Kwok-Hay So
E-LSTM: Efficient Inference of Sparse LSTM on Embedded Heterogeneous System. DAC 2019: 182 - [i7]Nan Meng, Hayden Kwok-Hay So, Xing Sun, Edmund Y. Lam:
High-dimensional Dense Residual Convolutional Neural Network for Light Field Reconstruction. CoRR abs/1910.01426 (2019) - [i6]Nina Engelhardt, Hayden Kwok-Hay So:
GraVF-M: Graph Processing System Generation for Multi-FPGA Platforms. CoRR abs/1910.07408 (2019) - 2018
- [j16]Wei Zhao
A Division-Free and Variable-Regularized LMS-Based Generalized Sidelobe Canceller for Adaptive Beamforming and Its Efficient Hardware Realization. IEEE Access 6: 64470-64485 (2018) - [j15]Manish Kumar Jaiswal
An Unified Architecture for Single, Double, Double-Extended, and Quadruple Precision Division. Circuits Syst. Signal Process. 37(1): 383-407 (2018) - [j14]Hayden Kwok-Hay So
Introduction to the Special Issue on Application-Specific Systems, Architectures and Processors. J. Signal Process. Syst. 90(1): 1-2 (2018) - [c48]Manish Kumar Jaiswal, Hayden Kwok-Hay So
Universal number posit arithmetic generator on FPGA. DATE 2018: 1159-1162 - [c47]Nina Engelhardt, C.-H. Dominic Hung, Hayden Kwok-Hay So
Performance-Driven System Generation for Distributed Vertex-Centric Graph Processing on Multi-FPGA Systems. FPL 2018: 215-218 - [c46]Manish Kumar Jaiswal, Hayden Kwok-Hay So
Architecture Generator for Type-3 Unum Posit Adder/Subtractor. ISCAS 2018: 1-5 - [c45]Vincent W. L. Tam, Chunkit Chui, Hayden Kwok-Hay So
Urban Farming in Myanmar: An Experiential Learning Project for Engineering and Science Students from Hong Kong and Myanmar. TALE 2018: 1185-1188 - [d1]Nan Meng, Kevin K. Tsia, Hayden Kwok-Hay So:
Human somatic label-free bright-field cell images. IEEE DataPort, 2018 - 2017
- [j13]Manish Kumar Jaiswal
Area-Efficient Architecture for Dual-Mode Double Precision Floating Point Division. IEEE Trans. Circuits Syst. I Regul. Pap. 64-I(2): 386-398 (2017) - [j12]Xing Sun
Computationally Efficient Hyperspectral Data Learning Based on the Doubly Stochastic Dirichlet Process. IEEE Trans. Geosci. Remote. Sens. 55(1): 363-374 (2017) - [j11]Philip Heng Wai Leong
The First 25 Years of the FPL Conference: Significant Papers. ACM Trans. Reconfigurable Technol. Syst. 10(2): 15:1-15:17 (2017) - [c44]Sam M. H. Ho, C.-H. Dominic Hung, Ho-Cheung Ng, Maolin Wang, Hayden Kwok-Hay So
A Parameterizable Activation Function Generator for FPGA-Based Neural Network Applications. FCCM 2017: 84 - [c43]Hayden Kwok-Hay So, John Wawrzynek:
OLAF'17: Third International Workshop on Overlay Architectures for FPGAs. FPGA 2017: 1 - [c42]Justin S. J. Wong
Ultra-low latency continuous block-parallel stream windowing using FPGA on-chip memory. FPT 2017: 56-63 - [c41]Sam M. H. Ho, Hayden Kwok-Hay So
NnCore: A parameterized non-linear function generator for machine learning applications in FPGAs. FPT 2017: 160-167 - [c40]Nina Engelhardt, Hayden Kwok-Hay So
Towards Flexible Automatic Generation of Graph Processing Gateware. HEART 2017: 5:1-5:6 - [c39]Nan Meng, Hayden Kwok-Hay So
Computational single-cell classification using deep learning on bright-field and phase images. MVA 2017: 190-193 - [i5]Hayden Kwok-Hay So, John Wawrzynek:
Proceedings of the 3rd International Workshop on Overlay Architectures for FPGAs (OLAF 2017). CoRR abs/1704.08802 (2017) - 2016
- [j10]Colin Yu Lin, Zhenghong Jiang, Cheng Fu, Hayden Kwok-Hay So
FPGA High-level Synthesis versus Overlay: Comparisons on Computation Kernels. SIGARCH Comput. Archit. News 44(4): 92-97 (2016) - [c38]Manish Kumar Jaiswal, Hayden Kwok-Hay So
Architecture for quadruple precision floating point division with multi-precision support. ASAP 2016: 239-240 - [c37]Xing Sun, Nelson H. C. Yung, Edmund Y. Lam
Unsupervised tracking with a low computational cost using the doubly stochastic Dirichlet process mixture model. Image Processing: Machine Vision Applications 2016: 1-8 - [c36]Nina Engelhardt, Hayden Kwok-Hay So
Vertex-Centric Graph Processing on FPGA. FCCM 2016: 92 - [c35]Hayden Kwok-Hay So
OLAF'16: Second International Workshop on Overlay Architectures for FPGAs. FPGA 2016: 1 - [c34]Nina Engelhardt, Hayden Kwok-Hay So
GraVF: A vertex-centric distributed graph processing framework on FPGAs. FPL 2016: 1-4 - [c33]Maolin Wang, Ho-Cheung Ng, Bob M. F. Chung, B. Sharat Chandra Varma, Manish Kumar Jaiswal, Kevin K. Tsia
Real-time object detection and classification for high-speed asymmetric-detection time-stretch optical microscopy on FPGA. FPT 2016: 261-264 - [c32]Xing Sun, Zhimin Xu, Nan Meng, Edmund Y. Lam
Data-driven light field depth estimation using deep Convolutional Neural Networks. IJCNN 2016: 367-374 - [c31]Xing Sun, Nan Meng, Zhimin Xu, Edmund Y. Lam
Sparse Hierarchical Nonparametric Bayesian learning for light field representation and denoising. IJCNN 2016: 3272-3279 - [c30]Manish Kumar Jaiswal, Hayden Kwok-Hay So
Taylor Series Based Architecture for Quadruple Precision Floating Point Division. ISVLSI 2016: 518-523 - [c29]Manish Kumar Jaiswal, Hayden Kwok-Hay So
Dual-mode double precision division architecture. MWSCAS 2016: 1-4 - [c28]Sam M. H. Ho, Maolin Wang, Ho-Cheung Ng, Hayden Kwok-Hay So
Towards FPGA-assisted spark: An SVM training acceleration case study. ReConFig 2016: 1-6 - [c27]Ho-Cheung Ng, Maolin Wang, Bob M. F. Chung, B. Sharat Chandra Varma
High-throughput cellular imaging with high-speed asymmetric-detection time-stretch optical microscopy under FPGA platform. ReConFig 2016: 1-6 - [p1]Hayden Kwok-Hay So
FPGA Overlays. FPGAs for Software Programmers 2016: 285-305 - [i4]Xing Sun, Nelson H. C. Yung, Edmund Y. Lam, Hayden Kwok-Hay So:
Consistency Analysis for the Doubly Stochastic Dirichlet Process. CoRR abs/1605.07358 (2016) - [i3]Hayden Kwok-Hay So, John Wawrzynek:
Proceedings of the 2nd International Workshop on Overlay Architectures for FPGAs (OLAF 2016). CoRR abs/1605.08149 (2016) - [i2]Ho-Cheung Ng, Cheng Liu, Hayden Kwok-Hay So:
A Soft Processor Overlay with Tightly-coupled FPGA Accelerator. CoRR abs/1606.06483 (2016) - 2015
- [j9]Manish Kumar Jaiswal, B. Sharat Chandra Varma, Hayden Kwok-Hay So
Configurable Architectures for Multi-Mode Floating Point Adders. IEEE Trans. Circuits Syst. I Regul. Pap. 62-I(8): 2079-2090 (2015) - [c26]Cheng Liu
Automatic Soft CGRA Overlay Customization for High-Productivity Nested Loop Acceleration on FPGAs. FCCM 2015: 101 - [c25]Philip Heng Wai Leong
Significant papers from the first 25 years of the FPL conference. FPL 2015: 1-3 - [c24]Junyi Xie, Xinyu Niu, Andy K. S. Lau, Kevin K. Tsia
Accelerated cell imaging and classification on FPGAs for quantitative-phase asymmetric-detection time-stretch optical microscopy. FPT 2015: 1-8 - [c23]Cheng Liu
QuickDough: A rapid FPGA loop accelerator design framework using soft CGRA overlay. FPT 2015: 56-63 - [c22]Manish Kumar Jaiswal, B. Sharat Chandra Varma, Hayden Kwok-Hay So
Architecture for Dual-Mode Quadruple Precision Floating Point Adder. ISVLSI 2015: 249-254 - [c21]Manish Kumar Jaiswal, Hayden Kwok-Hay So
Dual-mode double precision / two-parallel single precision floating point multiplier architecture. VLSI-SoC 2015: 213-218 - [i1]Cheng Liu, Ho-Cheung Ng, Hayden Kwok-Hay So:
Automatic Nested Loop Acceleration on FPGAs Using Soft CGRA Overlay. CoRR abs/1509.00042 (2015) - 2014
- [c20]Yuk-Ming Choi, Hayden Kwok-Hay So
Map-reduce processing of k-means algorithm with FPGA-accelerated computer cluster. ASAP 2014: 9-16 - [c19]Brandon Kyle Hamilton, Michael Inggs
Scheduling Mixed-Architecture Processes in Tightly Coupled FPGA-CPU Reconfigurable Computers. FCCM 2014: 240 - [c18]Brandon Kyle Hamilton, Michael Inggs
Mixed-architecture process scheduling on tightly coupled reconfigurable computers. FPL 2014: 1-4 - [e1]Jialin Chen, Wenbo Yin, Yuichiro Shibata, Lingli Wang, Hayden Kwok-Hay So, Yuchun Ma:
2014 International Conference on Field-Programmable Technology, FPT 2014, Shanghai, China, December 10-12, 2014. IEEE 2014, ISBN 978-1-4799-6245-7 [contents] - 2013
- [j8]Colin Yu Lin, Ngai Wong, Hayden Kwok-Hay So
Design space exploration for sparse matrix-matrix multiplication on FPGAs. Int. J. Circuit Theory Appl. 41(2): 205-219 (2013) - [c17]Cheng Liu
A Soft Coarse-Grained Reconfigurable Array Based High-level Synthesis Methodology: Promoting Design Productivity and Exploring Extreme FPGA Frequency. FCCM 2013: 228 - [c16]Ho-Cheung Ng, Yuk-Ming Choi, Hayden Kwok-Hay So
Direct virtual memory access from FPGA for high-productivity heterogeneous computing. FPT 2013: 458-461 - 2012
- [j7]Colin Yu Lin, Hayden Kwok-Hay So
Energy-efficient dataflow computations on FPGAs using application-specific coarse-grain architecture synthesis. SIGARCH Comput. Archit. News 40(5): 58-63 (2012) - [c15]Colin Yu Lin, Ngai Wong, Hayden Kwok-Hay So:
Operation scheduling and architecture co-synthesis for energy-efficient dataflow computations on FPGAs (abstract only). FPGA 2012: 270 - [c14]Changqing Xun, Mei Wen, Nan Wu, Chunyuan Zhang, Hayden Kwok-Hay So
Extending BORPH for shared memory reconfigurable computers. FPL 2012: 563-566 - [c13]Junying Chen, Alfred C. H. Yu
Design considerations of real-time adaptive beamformer for medical ultrasound research using FPGA and GPU. FPT 2012: 198-205 - 2011
- [j6]Chiu-Wah Ng, Ngai Wong, Hayden Kwok-Hay So
On IIR-based bit-stream multipliers. Int. J. Circuit Theory Appl. 39(2): 149-158 (2011) - [j5]Hayden Kwok-Hay So
Medical Ultrasound Imaging: To GPU or Not to GPU? IEEE Micro 31(5): 54-65 (2011) - [j4]Junying Chen, Billy Y. S. Yiu, Brandon Kyle Hamilton, Alfred C. H. Yu, Hayden Kwok-Hay So
Design space exploration of adaptive beamforming acceleration for bedside and portable medical ultrasound imaging. SIGARCH Comput. Archit. News 39(4): 20-25 (2011) - [c12]Colin Yu Lin, Hayden Kwok-Hay So
A Model for Peak Matrix Performance on FPGAs. FCCM 2011: 251 - [c11]Colin Yu Lin, Hayden Kwok-Hay So
A Model for Matrix Multiplication Performance on FPGAs. FPL 2011: 305-310 - 2010
- [j3]Chi Chiu Tsang, Hayden Kwok-Hay So
Dynamic power reduction of FPGA-based reconfigurable computers using precomputation. SIGARCH Comput. Archit. News 38(4): 87-92 (2010) - [j2]Sammy H. M. Kwok, Hayden Kwok-Hay So
Zero-configuration identity-based IP network encryptor. IEEE Trans. Consumer Electron. 56(2): 540-546 (2010) - [c10]Colin Yu Lin, Zheng Zhang
Design space exploration for sparse matrix-matrix multiplication on FPGAs. FPT 2010: 369-372
2000 – 2009
- 2009
- [c9]Colin Yu Lin, Ngai Wong, Hayden Kwok-Hay So
Operation scheduling for FPGA-based reconfigurable computers. FPL 2009: 481-484 - 2008
- [j1]Hayden Kwok-Hay So
A unified hardware/software runtime environment for FPGA-based reconfigurable computers using BORPH. ACM Trans. Embed. Comput. Syst. 7(2): 14:1-14:28 (2008) - [c8]Hayden Kwok-Hay So
Runtime Filesystem Support for Reconfigurable FPGA Hardware Processes in BORPH. FCCM 2008: 285-286 - [c7]Chiu-Wah Ng, Ngai Wong, Hayden Kwok-Hay So
Direct sigma-delta modulated signal processing in FPGA. FPL 2008: 475-478 - [c6]Hayden Kwok-Hay So
File system access from reconfigurable FPGA hardware processes in BORPH. FPL 2008: 567-570 - [c5]Chiu-Wah Ng, Ngai Wong, Hayden Kwok-Hay So
Quad-level bit-stream signal processing on FPGAs. FPT 2008: 309-312 - 2007
- [c4]Dejan Markovic, Chen Chang, Brian C. Richards, Hayden Kwok-Hay So
ASIC Design and Verification in an FPGA Environment. CICC 2007: 737-740 - 2006
- [c3]Hayden Kwok-Hay So
A unified hardware/software runtime environment for FPGA-based reconfigurable computers using BORPH. CODES+ISSS 2006: 259-264 - [c2]Hayden Kwok-Hay So
Improving Usability of FPGA-Based Reconfigurable Computers Through Operating System Support. FPL 2006: 1-6 - 2005
- [c1]Kevin Camera, Hayden Kwok-Hay So
An integrated debugging environment for reprogrammble hardware systems. AADEBUG 2005: 111-116
Coauthor Index
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