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Javier Jalle
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2010 – 2019
- 2017
- [j1]Gabriel Fernandez, Javier Jalle, Jaume Abella
, Eduardo Quiñones, Tullio Vardanega
Computing Safe Contention Bounds for Multicore Resources with Round-Robin and FIFO Arbitration. IEEE Trans. Computers 66(4): 586-600 (2017) - 2016
- [b1]Javier Jalle:
Improving time predictability of shared hardware resources in real-time multicore systems : emphasis on the space domain. Polytechnic University of Catalonia, Spain, 2016 - [c9]David Trilla
Improving Early Design Stage Timing Modeling in Multicore Based Real-Time Systems. RTAS 2016: 305-316 - [c8]Javier Jalle, Mikel Fernández
Contention-aware performance monitoring counte support for real-time MPSoCs. SIES 2016: 262-271 - [c7]Javier Jalle, Eduardo Quiñones, Jaume Abella
Data Bus Slicing for Contention-Free Multicore Real-Time Memory Systems. SIES 2016: 272-279 - 2015
- [c6]Gabriel Fernandez, Javier Jalle, Jaume Abella
Increasing confidence on measurement-based contention bounds for real-time round-robin buses. DAC 2015: 125:1-125:6 - [c5]Gabriel Fernandez, Javier Jalle, Jaume Abella
Resource usage templates and signatures for COTS multicore processors. DAC 2015: 155:1-155:6 - 2014
- [c4]Javier Jalle, Leonidas Kosmidis, Jaume Abella, Eduardo Quiñones, Francisco J. Cazorla:
Bus designs for time-probabilistic multicore processors. DATE 2014: 1-6 - [c3]Javier Jalle, Jaume Abella
AHRB: A high-performance time-composable AMBA AHB bus. RTAS 2014: 225-236 - [c2]Javier Jalle, Eduardo Quiñones
A Dual-Criticality Memory Controller (DCmc): Proposal and Evaluation of a Space Case Study. RTSS 2014: 207-217 - 2013
- [c1]Javier Jalle, Jaume Abella
Deconstructing bus access control policies for Real-Time multicores. SIES 2013: 31-38
Coauthor Index
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