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26th VDAT 2022: Jammu, India
- Ambika Prasad Shah
, Sudeb Dasgupta
VLSI Design and Test - 26th International Symposium, VDAT 2022, Jammu, India, July 17-19, 2022, Revised Selected Papers. Communications in Computer and Information Science 1687, Springer 2022, ISBN 978-3-031-21513-1
Devices and Technology
- Vivek Kumar
FEM Modeling of Thermal Aspect of Dielectric Inserted Under Source & Drain of 5 nm Nanosheet. 3-11 - Ajay Kumar
Differential Multi-bit Through Glass Vias for Three-Dimensional Integrated Circuits. 12-26 - Kingsuk Bag, Kislay Deep, Sharad Verma, Shashi Prabha Yadav, Manish Goswami, Kavindra Kandpal
Design of a Low-Voltage Charge-Sensitive Preamplifier Interfaced with Piezoelectric Tactile Sensor for Tumour Detection. 27-38 - Rahul Kumar Gupta
Design, Simulation and Optimization of Aluminum Nitride Based Accelerometer. 39-52 - Mahesh Vaidya
Low Loss Enabled Semi-superjunction 4H-SiC IGBT for High Voltage and Current Application. 53-64 - Khushwant Sehra
Implications of Field Plate HEMT Towards Power Performance at Microwave X - Band. 65-75 - Chanchal, Ajay Kumar Visvkarma, Hardhyan Sheoran
Investigation of Traps in AlGaN/GaN HEMT Epitaxial Structure Using Conductance Method. 76-84 - Aniket Gupta, Govind Bajpai, Navjeet Bagga, Shashank Banchhor, Sudeb Dasgupta, Anand Bulusu, Nitanshu Chauhan:
Unveiling the Impact of Interface Traps Induced on Negative Capacitance Nanosheet FET: A Reliability Perspective. 85-96 - Rajeewa Kumar Jaisawal
Impact of Temperature on NDR Characteristics of a Negative Capacitance FinFET: Role of Landau Parameter (α). 97-106 - Neelkamal, Sonal Yadav, Hemangee K. Kapoor:
i-MAX: Just-In-Time Wakeup of Maximally Gated Router for Power Efficient Multiple NoC. 107-117 - Shivendra Yadav, Deepak Joshi
Quantum Tunnelling and Themonic Emission, Transistor Simulation. 118-125 - Arvind Bisht
Electro-Thermal Analysis of Vertically Stacked Gate All Around Nano-sheet Transistor. 126-136
Sensors
- Rahul Sharma, Harshal B. Nemade:
Fabrication, Optimization and Testing of Photoconductively Tuned SAW Device Using CBD Method. 139-149 - Anuj Srivastava
High Resolution Temperature Sensor Signal Processing ASIC for Cryo-Cooler Electronics. 150-157
Analog/Mixed Signal
- Puneet Singh
Low Power, Wideband SiGe HBT LNA Covering 57-64 GHz Band. 161-171 - Mohd Asim Saeed
Four Differential Channels, Programmable Gain, Programmable Data Rate Delta Sigma ADC. 172-184 - Anshul Verma
Low Power Dual-Band Current Reuse-based LC-Voltage Controlled Oscillator with Shared Inductor for IoT Applications. 185-198 - Anmol Verma, Shubhang Srivastava, Ambika Prasad Shah
Aging Resilient and Energy Efficient Ring Oscillator for PUF Design. 199-211 - Neha Bajpai
A GaN Based Reverse Recovery Time Limiter Circuit Integrated with a Low Noise Amplifier. 212-221 - Divya Singh
Novel Configuration of Multi-mode Universal Shadow Filter Employing a New Active Block. 222-233 - Aranya Gupta
Highly Non-linear Feed-Forward Arbiter PUF Against Machine Learning Attacks. 234-248 - Bappaditya Mondal
An Online Testing Technique for the Detection of Control Nodes Displacement Faults (CNDF) in Reversible Circuits. 249-261 - S. Kavitha
An Approach Towards Analog In-Memory Computing for Energy-Efficient Adder in SRAM Array. 262-274
Digital Design
- Jitesh Choudhary
MANA: Multi-Application Mapping onto Mesh Network-on-Chip using ANN. 277-291 - Abhishek Maurya, Ayush Singh, Syed Farah Naz
Metastable SR Flip-Flop Based True Random Number Generator Using QCA Technology. 292-304 - Priyank H. Prajapati
Hardware Design of Two Stage Reference Free Adaptive Filter for ECG Denoising. 305-319 - Kunal Kranti Das, Aditya Japa, Deepika Gupta:
A Reconfigurable Arbiter PUF Based on VGSOT MTJ. 320-330 - Syed Farah Naz
Pass Transistor XOR Gate Based Radiation Hardened RO-PUF. 331-344 - Prateek Sinha, Aniket Sharma, Nilay Naharas, Syed Farah Naz
QCA Technology Based 8-Bit TRNG Design for Cryptography Applications. 345-357 - Shivangi Chandrakar, Kunal Kranti Das, Deepika Gupta, Manoj Kumar Majumder:
Signal Integrity and Power Loss Analysis for Different Bump Structures in Cylindrical TSV. 358-372 - Subrata Das
Reliability Aware Global Routing of Graphene Nanoribbon Based Interconnect. 373-386 - Hariveer Inumarty, M. Mohamed Asan Basiri:
Low Cost Hardware Design of ECC Scalar Multiplication. 387-396 - Anishetti Venkatesh
Scalable Construction of Formal Error Guaranteed LUT-Based Approximate Multipliers with Analytical Worst-Case Error Bound. 397-407 - Kanika Monga, Eesha Karnawat, Nitin Chaturvedi, S. Gurunarayanan:
Design of a Programmable Delay Line with On-Chip Calibration to Achieve Immunity Against Process Variations. 408-419 - Panasa Srikanth
High Performance Ternary Full Adder in CNFET-Memristor Logic Technology. 420-434 - Pooja Choudhary
Synthesis of LUT Based Approximating Adder Circuits with Formal Error Guarantees. 435-449
Emerging Technologies and Memory
- Shubham Singhania
CAR: Community Aware Graph Reordering for Efficient Cache Utilization in Graph Analytics. 453-467 - Wasi Uddin, Ankit Bende
Indigenous Fab-Lab Hybrid Device Integration for Phase Change Memory for In-Memory Computing. 468-477 - Shalu Saini, Anil Lodhi
Resistive Switching Behavior of TiO2/(PVP: MoS2) Nanocomposite Bilayer Hybrid RRAM. 478-485 - Pramod Kumar Bharti
RTQCC-14T: Radiation Tolerant Quadruple Cross Coupled Robust SRAM Design for Radiation Prone Environments. 486-498 - Ashwin Sanjay Lele, Srivatsava Jandhyala
Disrupting Low-Write-Energy vs. Fast-Read Dilemma in RRAM to Enable L1 Instruction Cache. 499-512
System Design
- M. K. Aparna Nair
Implementation and Analysis of Convolution Image Filtering with RISC-V Based Architecture. 515-526 - Ramesh Kumar, Ajay Kumar Singh, Chiragkumar Patel, S. Vinay Kumar, Himanshu N. Patel, B. Saravana Kumar:
Development of Distributed Controller for Electronic Beam Steering Using Indigenous Rad-Hard ASIC. 527-539 - Chiragkumar B. Patel, Ganesh A. Mulay, Himanshu N. Patel, Pooja Dhankher:
Tile Serial Protocol (TSP) ASIC for Distributed Controllers of Space-Borne RADAR. 540-550 - Narnindi Ramani
A Deep Dive into CORDIC Architectures to Implement Trigonometric Functions. 551-561 - Kailash Prasad
Impact of Operand Ordering in Approximate Multiplication in Neural Network and Image Processing Applications. 562-572 - Rudresh Pratap Singh
An Overlap-and-Add Based Time Domain Acceleration of CNNs on FPGA-CPU Systems. 573-583 - Gaurav Kumar
Low Cost Implementation of Deep Neural Network on Hardware. 584-594
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