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Soumya J.
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2020 – today
- 2024
- [c35]Mekala Bindu Bhargavi, Grandhala Sri Sai Harshith, Sri Parameswaran, Soumya J.:
Optimizing LU Decomposition with RISC-V Based Hardware Acceleration. ISVLSI 2024: 210-215 - [c34]Mekala Bindu Bhargavi, Sai Siddharth Rokkam, Sri Parameswaran, Soumya J.:
Automated Design and Configuration of RISC-V based NoC-MPSoC Framework on FPGA. VDAT 2024: 1-6 - [c33]N. Vamshi Krishna, Anushka Chaudhary, Soumya J.:
FGG: Feedback Guided Generation to Accelerate Functional Coverage Closure on Network-on-Chip Processors. VLSID 2024: 702-707 - 2023
- [c32]N. Vamshi Krishna, Jay P. Shah, Soumya J.
:
Improving the Functional Coverage Closure of Network-on-Chip using Genetic Algorithm. ISCAS 2023: 1-5 - [c31]N. Vamshi Krishna, Rahul Tripathy, Joshitha Marripudi, Soumya J.
Improving Functional Coverage of Network-On-Chip Using Differential Evolution. PRIME 2023: 369-372 - [c30]N. Vamshi Krishna, Aruna, Soumya J.
Improving the Functional Coverage Closure of Network-on-Chip using Particle Swarm Optimization. SMACD 2023: 1-4 - 2022
- [j14]Jagadheesh Samala
Reinforcement Learning Based Fault-Tolerant Routing Algorithm for Mesh Based NoC and Its FPGA Implementation. IEEE Access 10: 44724-44737 (2022) - [j13]Jagadheesh Samala
NoC Application Mapping Optimization Using Reinforcement Learning. ACM Trans. Design Autom. Electr. Syst. 27(6): 55:1-55:16 (2022) - [c29]Jitesh Choudhary
MANA: Multi-Application Mapping onto Mesh Network-on-Chip using ANN. VDAT 2022: 277-291 - [c28]M. K. Aparna Nair, Police Manoj Kumar Reddy, Y. L. Abijith, Venkatesh Rajagopalan, Soumya J.
Hardware Implementation of Network Interface Architecture for RISC-V based NoC-MPSoC Framework. VLSID 2022: 86-91 - 2021
- [j12]P. Veda Bhanu
Flexible Spare Core Placement in Torus Topology Based NoCs and Its Validation on an FPGA. IEEE Access 9: 45935-45954 (2021) - [j11]P. Veda Bhanu
Fault-Tolerant Application-Specific Topology-Based NoC and Its Prototype on an FPGA. IEEE Access 9: 76759-76779 (2021) - [j10]P. Veda Bhanu
Fault-Tolerant Application Mapping on Mesh-of-Tree based Network-on-Chip. J. Syst. Archit. 116: 102026 (2021) - [c27]Prabhat Kumar Rai
Angle and Height Estimation Technique for Aerial Vehicles using mmWave FMCW Radar. COMSNETS 2021: 104-108 - [c26]Jyoti Bhatia, Aveen Dayal, Ajit Jha, Santosh Kumar Vishvakarma, Soumya J.
Object Classification Technique for mmWave FMCW Radars using Range-FFT Features. COMSNETS 2021: 111-115 - [c25]M. K. Aparna Nair, P. Veda Bhanu, Soumya J.
Architectural Implementation of a Reconfigurable NoC Design for Multi-Applications. DSD 2021: 139-142 - [c24]Jitesh Choudhary
RAMAN: Reinforcement Learning Inspired Algorithm for Mapping Applications onto Mesh Network-on-Chip. SLIP 2021: 52-58 - 2020
- [c23]P. Veda Bhanu, Chetan Vudadha, Soumya J.:
FILA: Fault-Model for Interconnection Links in Application-Specific Network-on-Chip Design. ISCAS 2020: 1-5 - [c22]Hari Bhusal, Pankaj Khatiwada
A Self-Powered Long-range Wireless IoT Device based on LoRaWAN. iSES 2020: 242-245 - [c21]Jagadheesh Samala, Harshvardhan C. Takawale
Fault-Tolerant Routing Algorithm for Mesh based NoC using Reinforcement Learning. VDAT 2020: 1-6
2010 – 2019
- 2019
- [j9]P. Veda Bhanu, Pranav Venkatesh Kulkarni, Soumya J.
Butterfly-Fat-Tree topology based fault-tolerant Network-on-Chip design using particle swarm optimisation. J. Exp. Theor. Artif. Intell. 31(5): 781-799 (2019) - [j8]P. Veda Bhanu, Pranav Venkatesh Kulkarni, Soumya J.
Fault-Tolerant Network-on-Chip Design with Flexible Spare Core Placement. ACM J. Emerg. Technol. Comput. Syst. 15(1): 5:1-5:23 (2019) - [c20]P. Veda Bhanu, Soumya J.
Fault-Tolerant Application-Specific Network-on-Chip Design using Discrete Particle Swarm Optimization. ICIIS 2019: 500-505 - [c19]Joshua Pushparaj, P. Veda Bhanu, Soumya J.
A Link Fault Tolerant Routing Algorithm for Mesh of Tree Based Network-on-Chips. iSES 2019: 181-184 - [c18]P. Veda Bhanu
FPGA Implementation of Novel Routing Algorithm for Butterfly-Fat-Tree Topology based NoC Design. PRIME 2019: 69-72 - [c17]P. Veda Bhanu
Multi-application Based Fault-Tolerant Network-on-Chip Design for Mesh Topology Using Reconfigurable Architecture. VDAT 2019: 442-454 - [c16]Mohit Upadhyay, Monil Shah, P. Veda Bhanu, Soumya J.
Multi-application Based Network-on-Chip Design for Mesh-of-Tree Topology Using Global Mapping and Reconfigurable Architecture. VLSID 2019: 527-528 - [c15]Rolf Arne Kjellby, Linga Reddy Cenkeramaddi
Long-range & Self-powered IoT Devices for Agriculture & Aquaponics Based on Multi-hop Topology. WF-IoT 2019: 545-549 - 2018
- [c14]Rolf Arne Kjellby, Linga Reddy Cenkeramaddi
Self-powered IoT Device based on Energy Harvesting for Remote Applications. ANTS 2018: 1-4 - [c13]Mohit Upadhyay, Monil Shah, P. Veda Bhanu, Soumya J.
Fault Tolerant Routing Methodology for Mesh-of-Tree based Network-on-Chips using Local Reconfiguration. HPCS 2018: 570-576 - [c12]Henning Idsoe, Linga Reddy Cenkeramaddi
Sensor Data Compression Based on Re-Quantization of Sensor Data. iSES 2018: 98-103 - [c11]Linga Reddy Cenkeramaddi
Design of Software and Data Analytics for Self-Powered Wireless IoT Devices. iSES 2018: 118-123 - [c10]P. Veda Bhanu, Pranav Venkatesh Kulkarni, Soumya J.
Torus Topology based Fault-Tolerant Network-on-Chip Design with Flexible Spare Core Placement. PRIME 2018: 97-100 - [c9]Divvya Sinha, Ashmita Roy, Kunchakuri Varun Kumar, Pranav Venkatesh Kulkarni, Soumya J.
Dn-FTR: Fault-tolerant routing algorithm for Mesh based network-on-chip. RAIT 2018: 1-5 - [c8]Mohit Upadhyay, Monil Shah, P. Veda Bhanu, Soumya J.
A Novel Fault-Tolerant Routing Technique for Mesh-of-Tree based Network-on-Chip Design. TENCON 2018: 2378-2383 - [c7]P. Veda Bhanu, Pranav Venkatesh Kulkarni, Sarthak Jain, Soumya J.
Fault-Tolerant Network-on-Chip Design for Mesh-of-Tree Topology Using Particle Swarm Optimization. TENCON 2018: 2384-2389 - [c6]Monil Shah, Mohit Upadhyay, P. Veda Bhanu, Soumya J.
A Novel Fault-Tolerant Routing Algorithm for Mesh-of-Tree Based Network-on-Chips. VDAT 2018: 446-459 - 2017
- [j7]Soumya J.
Multi-Application Mapping onto a Switch-Based Reconfigurable Network-on-Chip Architecture. J. Circuits Syst. Comput. 26(11): 1750174:1-1750174:31 (2017) - [c5]Parth Shah, Kanniganti Abhishek, Soumya J.
Fault-tolerant application specific Network-on-Chip design. ISED 2017: 1-5 - [c4]Grandhi Sai Anirudh, Soumya J.
Routing Algorithm for Application-Specific Network-on-Chip with Irregular Core Sizes. iNIS 2017: 56-60 - 2016
- [j6]Sandeep D'Souza, Soumya J.
Integrated Mapping and Synthesis Techniques for Network-on-Chip Topologies with Express Channels. ACM Trans. Archit. Code Optim. 12(4): 40:1-40:26 (2016) - 2015
- [j5]Soumya J.
Area-performance trade-off in floorplan generation of Application-Specific Network-on-Chip with soft cores. J. Syst. Archit. 61(1): 1-11 (2015) - [j4]Soumya J.
Integrated core selection and mapping for mesh based Network-on-Chip design with irregular core sizes. J. Syst. Archit. 61(9): 410-422 (2015) - [c3]Sandeep D'Souza, Soumya J.
A constructive heuristic for application mapping onto an express channel based Network-on-Chip. VDAT 2015: 1-6 - 2014
- [j3]Soumya J.
Multi-Application Network-on-Chip Design using Global Mapping and Local Reconfiguration. ACM Trans. Reconfigurable Technol. Syst. 7(2): 7:1-7:24 (2014) - [c2]Soumya J.
A locally reconfigurable Network-on-Chip architecture and application mapping onto it. VDAT 2014: 1-6 - 2013
- [j2]Soumya J.
Application-Specific Network-on-Chip synthesis with flexible router Placement. J. Syst. Archit. 59(7): 361-371 (2013) - 2012
- [j1]Santanu Kundu, Soumya J.
Design and evaluation of Mesh-of-Tree based Network-on-Chip using virtual channel router. Microprocess. Microsystems 36(6): 471-488 (2012) - 2011
- [c1]Soumya J.
Flexible Router Placement with Link Length and Port Constraints for Application-Specific Network-on-Chip Synthesis. ISVLSI 2011: 341-342
Coauthor Index
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