Abstract
To conquer the drawback of von Neumann architecture, research has been carried out on the computational methods in the memory array itself to achieve near-memory or in-memory computations (IMC). This paper for the first time proposed an analog IMC approach for full adder design using 8\(^+\)T Static Random Access Memories (SRAM). In conventional FA, addition is executed as a sequence of digital boolean operations inside the memory array and there is a need for external logic gates to compute the FA outputs. The proposed analog adder exploits the bit-line voltage discharge (V\(_{BL}\)) with respect to the data stored in the 8\(^+\)T memory cell for the bit addition. The bit-line discharge voltage is accumulated using a voltage accumulation circuit (VAC) and acts as an input to an analog to digital converter (ADC). The digital output obtained is the Sum of a single bit FA. Multi-bit FA is computed from this single-bit analog FA. Extensive simulation results, referring to an industrial hardware-calibrated UMC 65-nm CMOS technology indicate 27\(\times \) improvement in power and 36\(\times \) improvements in throughput leading to a reduction of 972\(\times \) in energy-delay product.
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Kavitha, S., Vishvakarma, S.K., Reniwal, B.S. (2022). An Approach Towards Analog In-Memory Computing for Energy-Efficient Adder in SRAM Array. In: Shah, A.P., Dasgupta, S., Darji, A., Tudu, J. (eds) VLSI Design and Test. VDAT 2022. Communications in Computer and Information Science, vol 1687. Springer, Cham. https://doi.org/10.1007/978-3-031-21514-8_23
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