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Chandan Kumar Jha 0001
Person information
- affiliation: Deutsches Forschungszentrum für Künstliche Intelligenz (DFKI), Bremen, Germany
- affiliation (former): Indian Institute of Technology Bombay, Mumbai, India
- affiliation: Indian Institute of Technology Gandhinagar, Gujarat, India
Other persons with the same name
- Chandan Kumar Jha 0002
— Indian Institute of Technology Patna, India
- Chandan Kumar Jha 0003
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2020 – today
- 2024
- [j10]Sajjad Parvin, Sallar Ahmadi-Pour, Chandan Kumar Jha, Frank Sill Torres, Rolf Drechsler:
Lower the RISC: Designing optical-probing-attack-resistant cores. Microprocess. Microsystems 111: 105121 (2024) - [j9]Chandan Kumar Jha
cecApprox: Enabling Automated Combinational Equivalence Checking for Approximate Circuits. IEEE Trans. Circuits Syst. I Regul. Pap. 71(7): 3282-3293 (2024) - [j8]Chandan Kumar Jha
veriSIMPLER: An Automated Formal Verification Methodology for SIMPLER MAGIC Design Style Based In-Memory Computing. IEEE Trans. Circuits Syst. I Regul. Pap. 71(9): 4169-4179 (2024) - [c26]Simranjeet Singh, Chandan Kumar Jha, Ankit Bende, Vikas Rana, Sachin B. Patkar, Rolf Drechsler, Farhad Merchant:
MemSPICE: Automated Simulation and Energy Estimation Framework for MAGIC-Based Logic-in-Memory. ASPDAC 2024: 282-287 - [c25]Khushboo Qayyum
Late Breaking Results: LLM-assisted Automated Incremental Proof Generation for Hardware Verification. DAC 2024: 349:1-349:2 - [c24]Muhammad Hassan, Sallar Ahmadi-Pour, Khushboo Qayyum, Chandan Kumar Jha, Rolf Drechsler:
LLM-Guided Formal Verification Coupled with Mutation Testing. DATE 2024: 1-2 - [c23]Sajjad Parvin, Chandan Kumar Jha, Frank Sill Torres, Rolf Drechsler:
Hidden Cost of Circuit Design with RFETs. DATE 2024: 1-2 - [c22]Mohamed A. Nadeem
Polynomial Formal Verification of Approximate Adders with Constant Cutwidth. ETS 2024: 1-6 - [c21]Simranjeet Singh, Ankit Bende, Chandan Kumar Jha, Vikas Rana, Rolf Drechsler, Sachin B. Patkar, Farhad Merchant:
In-Memory Mirroring: Cloning Without Reading. VLSI-SoC 2024: 1-6 - [c20]Ankit Bende, Simranjeet Singh, Chandan Kumar Jha, Tim Kempen, Felix Cüppers, Christopher Bengel, Andre Zambanini, Dennis Nielinger
Experimental Validation of Memristor-Aided Logic Using 1T1R TaOx RRAM Crossbar Array. VLSID 2024: 565-570 - [c19]Chandan Kumar Jha, Sallar Ahmadi-Pour, Rolf Drechsler:
Input Distribution Aware Library of Approximate Adders Based on Memristor-Aided Logic. VLSID 2024: 577-582 - [i7]Simranjeet Singh, Ankit Bende, Chandan Kumar Jha, Vikas Rana, Rolf Drechsler, Sachin B. Patkar, Farhad Merchant:
In-Memory Mirroring: Cloning Without Reading. CoRR abs/2407.02921 (2024) - 2023
- [j7]Simranjeet Singh
Should We Even Optimize for Execution Energy? Rethinking Mapping for MAGIC Design Style. IEEE Embed. Syst. Lett. 15(4): 230-233 (2023) - [j6]Chandan Kumar Jha
MARADIV: Library of MAGIC-Based Approximate Restoring Array Divider Benchmark Circuits for In-Memory Computing Using Memristors. IEEE Trans. Circuits Syst. II Express Briefs 70(7): 2635-2639 (2023) - [j5]Chandan Kumar Jha
Single Exact Single Approximate Adders and Single Exact Dual Approximate Adders. IEEE Trans. Very Large Scale Integr. Syst. 31(7): 907-916 (2023) - [c18]Sajjad Parvin, Sallar Ahmadi-Pour, Chandan Kumar Jha, Frank Sill Torres, Rolf Drechsler:
Lo-RISK: Design of a Low Optical Leakage and High Performance RISC-V Core. COINS 2023: 1-4 - [c17]Tom Glint, Chandan Kumar Jha, Manu Awasthi, Joycee Mekie:
Analysis of Quantization Across DNN Accelerator Architecture Paradigms. DATE 2023: 1-2 - [c16]Tom Glint, Chandan Kumar Jha, Manu Awasthi, Joycee Mekie:
Analysis of Conventional, Near-Memory, and In-Memory DNN Accelerators. ISPASS 2023: 349-351 - [c15]Chandan Kumar Jha, Rolf Drechsler:
Benchmarking Multiplier Architectures for MAGIC Based In-Memory Computing. NEWCAS 2023: 1-5 - [c14]Simranjeet Singh
Finite State Automata Design using 1T1R ReRAM Crossbar. NEWCAS 2023: 1-5 - [i6]Simranjeet Singh
Finite State Automata Design using 1T1R ReRAM Crossbar. CoRR abs/2304.13552 (2023) - [i5]Simranjeet Singh, Chandan Kumar Jha, Ankit Bende
Should We Even Optimize for Execution Energy? Rethinking Mapping for MAGIC Design Style. CoRR abs/2307.03669 (2023) - [i4]Simranjeet Singh
MemSPICE: Automated Simulation and Energy Estimation Framework for MAGIC-Based Logic-in-Memory. CoRR abs/2309.04868 (2023) - [i3]Ankit Bende, Simranjeet Singh
Experimental Validation of Memristor-Aided Logic Using 1T1R TaOx RRAM Crossbar Array. CoRR abs/2310.10460 (2023) - 2022
- [c13]Neelam Sharma
Data-Aware Cache Management for Graph Analytics. DATE 2022: 843-848 - [c12]Chandan Kumar Jha, Arup Lal Chakraborty:
A fibre Bragg grating sensor-based instrumented glove for virtual rehabilitation applications. OFC 2022: 1-3 - [c11]Anishetti Venkatesh
Scalable Construction of Formal Error Guaranteed LUT-Based Approximate Multipliers with Analytical Worst-Case Error Bound. VDAT 2022: 397-407 - [c10]Shubham Singhania
CAR: Community Aware Graph Reordering for Efficient Cache Utilization in Graph Analytics. VDAT 2022: 453-467 - [i2]Tom Glint, Chandan Kumar Jha, Manu Awasthi, Joycee Mekie:
A Fresh Perspective on DNN Accelerators by Performing Holistic Analysis Across Paradigms. CoRR abs/2208.05294 (2022) - 2021
- [j4]Chandan Kumar Jha
Zero Aware Configurable Data Encoding by Skipping Transfer for Error Resilient Applications. IEEE Trans. Circuits Syst. I Regul. Pap. 68(8): 3337-3350 (2021) - [j3]Chandan Kumar Jha
Analysis of Worst-Case Data Dependent Temporal Approximation in Floating Point Units. IEEE Trans. Circuits Syst. II Express Briefs 68(2): 767-771 (2021) - [c9]Chandan Kumar Jha, Sumit Walia, Gagan Kanojia, Joycee Mekie:
FPCAM: Floating Point Configurable Approximate Multiplier for Error Resilient Applications. ISCAS 2021: 1-5 - [i1]Chandan Kumar Jha, Shreyas Singh, Riddhi Thakker, Manu Awasthi, Joycee Mekie:
Zero Aware Configurable Data Encoding by Skipping Transfer for Error Resilient Applications. CoRR abs/2105.07432 (2021) - 2020
- [j2]Chandan Kumar Jha
Energy and Error Analysis Framework for Approximate Computing in Mobile Applications. IEEE Trans. Circuits Syst. II Express Briefs 67-II(2): 385-389 (2020) - [c8]Chandan Kumar Jha, Kailash Prasad
FPAD: A Multistage Approximation Methodology for Designing Floating Point Approximate Dividers. ISCAS 2020: 1-5 - [c7]Chandan Kumar Jha, Kailash Prasad
SEDAAF: FPGA Based Single Exact Dual Approximate Adders for Approximate Processors. ISCAS 2020: 1-5 - [c6]Ankita Nandi, Chandan Kumar Jha, Joycee Mekie:
Tunable Inexact Subtracters for Division in Image Processing Applications. MWSCAS 2020: 1100-1103
2010 – 2019
- 2019
- [c5]Ankita Nandi, Chandan Kumar Jha, Joycee Mekie:
Should We Code Differently When Using Approximate Circuits? APCCAS 2019: 37-40 - [c4]Chandan Kumar Jha, Joycee Mekie:
SEDA - Single Exact Dual Approximate Adders for Approximate Processors. DAC 2019: 237 - [c3]Chandan Kumar Jha, Joycee Mekie:
Design of Novel CMOS Based Inexact Subtractors and Dividers for Approximate Computing: An In-Depth Comparison with PTL Based Designs. DSD 2019: 174-181 - [c2]Chandan Kumar Jha, Ankita Nandi, Joycee Mekie:
Quality Tunable Approximate Adder for Low Energy Image Processing Applications. ICECS 2019: 642-645 - 2018
- [c1]Chandan Kumar Jha, Arup Lal Chakraborty:
A Fiber Bragg Grating Strain Sensor-Based Glove to Accurately Measure the Bend Angle of the Finger Flexed at the Proximal Interphalangeal Joints. IEEE SENSORS 2018: 1-4 - 2016
- [j1]Vinay Kumar
A Novel Methodology for Design of Cyclic Combinational Circuits. J. Low Power Electron. 12(3): 205-217 (2016)
Coauthor Index
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last updated on 2024-12-11 20:40 CET by the dblp team
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