default search action
18th FPL 2008: Heidelberg, Germany
- FPL 2008, International Conference on Field Programmable Logic and Applications, Heidelberg, Germany, 8-10 September 2008. IEEE 2008, ISBN 978-1-4244-1961-6
- Ivo Bolsens:
FPGA: The future platform for transforming, transporting and computing data. 1 - L. Musa:
FPGAS in high energy physics experiments at CERN. 2 - Dan Werthimer:
Searching for ET with FPGA'S. 3 - O. Wohlmuth:
Keynote: High performance computing based on FPGAS. 4
Modelling
- Martin Danek
, Jiri Kadlec, Roman Bartosinski, Lukas Kohout:
Increasing the level of abstraction in FPGA-based designs. 5-10 - Spyridon Ninos, Apostolos Dollas:
Modeling recursion data structures for FPGA-based implementation. 11-16 - Enno Lübbers, Marco Platzner
A portable abstraction layer for hardware threads. 17-22
Encryption Applications
- Yohei Hori
Bitstream encryption and authentication with AES-GCM in dynamically reconfigurable systems. 23-28 - Anh Tuan Hoang, Katsuhiro Yamazaki, Shigeru Oyanagi:
Three-stage pipeline implementation for SHA2 using data forwarding. 29-34 - Atsushi Miyamoto, Naofumi Homma, Takafumi Aoki, Akashi Satoh:
Chosen-message SPA attacks against FPGA-based RSA hardware implementations. 35-40
Networks on Chip I
- Graham Schelle, Dirk Grunwald:
Exploring FPGA network on chip implementations across various application and network loads. 41-46 - Ricardo S. Ferreira, Marcone Laure, Mateus B. Rutzig
Reducing interconnection cost in coarse-grained dynamic computing through multistage network. 47-52 - Henrique C. Freitas
NOC architecture design for multi-cluster chips. 53-58
Analysis of Reconfigurability
- Paul Schumacher, Pradip Jha:
Fast and accurate resource estimation of RTL-based designs targeting FPGAS. 59-64 - Tomasz S. Czajkowski, Stephen Dean Brown:
Fast toggle rate computation for FPGA circuits. 65-70 - Ricardo Chaves
On-the-fly attestation of reconfigurable hardware. 71-76
Image and Video Processing
- Takashi Saegusa, Tsutomu Maruyama, Yoshiki Yamaguchi:
How fast is an FPGA in image processing? 77-82 - Theepan Moorthy, Andy Ye:
A scalable computing and memory architecture for variable block size motion estimation on Field-Programmable Gate Arrays. 83-88 - Oliver Bowen, Christos-Savvas Bouganis
Real-time image super resolution using an FPGA. 89-94
FPGA Architecture
- Shakith Fernando, Xiaolei Chen, Yajun Ha:
sFPGA - A scalable switch based FPGA architecture and design methodology. 95-100 - Pongstorn Maidee
FPGA family composition and effects of specialized blocks. 101-106 - Kazutoshi Kobayashi, Yohei Kume, Cam Lai Ngo, Yuuri Sugihara, Hidetoshi Onodera:
A variation-aware constant-order optimization scheme utilizing delay detectors to search for fastest paths on FPGAS. 107-112
Dynamic Reconfiguration
- Sándor P. Fekete, Tom Kamphans, Nils Schweer, Christopher Tessars, Jan van der Veen, Josef Angermeier, Dirk Koch, Jürgen Teich:
No-break dynamic defragmentation of reconfigurable devices. 113-118 - Dirk Koch, Christian Beckhoff, Jürgen Teich:
ReCoBus-Builder - A novel tool and technique to build statically and dynamically reconfigurable systems for FPGAS. 119-124 - Jorge Surís, Cameron D. Patterson, Peter Athanas:
An efficient run-time router for connecting modules in FPGAS. 125-130
Search and Matching Acceleration
- Norio Yamagaki, Reetinder P. S. Sidhu, Satoshi Kamiya:
High-speed regular expression matching engine using multi-character NFA. 131-136 - Hoang Le, Weirong Jiang
Scalable high-throughput SRAM-based architecture for IP-lookup using FPGA. 137-142 - Song Sun, Joseph Zambreno:
Mining Association Rules with systolic trees. 143-148
Reconfigurable ASIP Design
- José Luis Núñez-Yáñez
A configurable and programmable motion estimation processor for the H.264 video codec. 149-154 - Tobias Krawutschke:
A flexible and reliable embedded system for detector control in a high energy physics experiment. 155-160 - Sylvain Guilley, Laurent Sauvage, Jean-Luc Danger, Philippe Hoogvorst:
Area optimization of cryptographic co-processors implemented in dual-rail with precharge positive logic. 161-166
Compilers for Reconfigurable Architectures
- Ozana Silvia Dragomir, Todor P. Stefanov
Loop unrolling and shifting for reconfigurable architectures. 167-172 - Andrew Putnam
CHiMPS: A C-level compilation flow for hybrid CPU-FPGA architectures. 173-178 - Qiang Liu, George A. Constantinides, Konstantinos Masselos, Peter Y. K. Cheung:
Combining data reuse exploitationwith data-level parallelization for FPGA targeted hardware compilation: A geometric programming framework. 179-184
Novel Applications
- Christiane Beuschel, Hans-Jörg Pfleiderer:
FPGA implementation of a flexible decoder for long LDPC codes. 185-190 - Brian Leung, Yan Pan, Christopher L. Schroeder, Seda Ogrenci Memik, Gokhan Memik, Mitra J. Z. Hartmann:
Towards an "early neural circuit simulator": A FPGA implementation of processing in the rat whisker system. 191-196 - Horácio C. Neto
Decimal multiplier on FPGA using embedded binary multipliers. 197-202
Reconfigurable Processors
- Lars Bauer, Muhammad Shafique, Jörg Henkel:
A computation- and communication- infrastructure for modular special instructions in a dynamically reconfigurable processor. 203-208 - Young-Su Kwon, Bontae Koo, Nak-Woong Eum:
Application-adaptive reconfiguration of memory address shuffler for FPGA-embedded instruction-set processor. 209-214 - Toru Sano, Masaru Kato, Satoshi Tsutsumi, Yohei Hasegawa, Hideharu Amano:
Instruction buffer mode for multi-context Dynamically Reconfigurable Processors. 215-220
Analysis of Reconfigurability II
- Andrew Lam, Steven J. E. Wilton, Philip Heng Wai Leong
An analytical model describing the relationships between logic architecture and FPGA density. 221-226 - Chun Hok Ho, Philip Heng Wai Leong
Rapid estimation of power consumption for hybrid FPGAs. 227-232 - Kristofer Vorwerk, Madhu Raman, Julien Dunoyer, Yaun-Chung Hsu, Arun Kundu, Andrew A. Kennings:
A technique for minimizing power during FPGA placement. 233-238
Random Number Generation & PLL
- David B. Thomas, Wayne Luk:
Sampling from the exponential distribution using independent Bernoulli variates. 239-244 - Viktor Fischer, Florent Bernard, Nathalie Bochard, Michal Varchola:
Enhancing security of ring oscillator-based trng implemented in FPGA. 245-250 - Martin Kumm, M. Shahab Sanjari
Digital hilbert transformers for FPGA-based phase-locked loops. 251-256
Networks on Chip II
- Matthew Shelburne, Cameron D. Patterson, Peter Athanas, Mark Jones, Brian S. Martin, Ryan Fong:
Metawire: Using FPGA configuration circuitry to emulate a Network-on-Chip. 257-262 - Tamas Malek, Tomás Martínek
GICS: Generic interconnection system. 263-268 - Daihan Wang, Hiroki Matsutani, Hideharu Amano, Michihiro Koibuchi:
A link removal methodology for Networks-on-Chip on reconfigurable systems. 269-274
Codesign
- Yuet Ming Lam, José Gabriel F. Coutinho, Wayne Luk, Philip Heng Wai Leong
Mapping and scheduling with task clustering for heterogeneous computing systems. 275-280 - Holger Lange, Andreas Koch:
Low-latency high-bandwidth HW/SW communication in a virtual memory environment. 281-286
FPGA Application in High Energy Physics
- Ming Liu, Johannes Lang, Shuo Yang, Tiago Perez, Wolfgang Kuehn, Hao Xu, Dapeng Jin, Qiang Wang, Lu Li, Zhen'An Liu, Zhonghai Lu, Axel Jantsch
ATCA-based computation platform for data acquisition and triggering in particle physics experiments. 287-292 - Jan de Cuveland, Felix Rettig, Venelin Angelov, Volker Lindenstruth:
An FPGA-based high-speed, low-latency trigger processor for high-energy physics. 293-298
Reconfigurable Processor Arrays
- Matthew A. Watkins, Mark J. Cianchetti, David H. Albonesi:
Shared reconfigurable architectures for CMPS. 299-304 - Takashi Nishimura, Keiichiro Hirai, Yoshiki Saito, Takuro Nakamura, Yohei Hasegawa, Satoshi Tsutsumi, Vasutan Tunbunheng, Hideharu Amano:
Power reduction techniques for Dynamically Reconfigurable Processor Arrays. 305-310
Tools for FPGA Design
- Kevin Camera, Robert W. Brodersen:
An integrated debugging environment for FPGA computing platforms. 311-316 - Benoît Badrignans, Reouven Elbaz, Lionel Torres:
Secure FPGA configuration architecture preventing system downgrade. 317-322 - Radu Andrei Stefan, Sorin Dan Cotofana
Bitstream compression techniques for Virtex 4 FPGAs. 323-328
High Performance Computing for Financial and Biological Modelling
- Alexander Kaganov, Paul Chow, Asif Lakhany:
FPGA acceleration of Monte-Carlo based credit derivative pricing. 329-334 - Nathan A. Woods, Tom VanCourt:
FPGA acceleration of quasi-Monte Carlo in finance. 335-340 - Bharat Sukhwani, Martin C. Herbordt:
Acceleration of a production rigid molecule docking code. 341-346
SPP1148 booth
- Josef Angermeier, Mateusz Majer, Jürgen Teich, Lars Braun, Tobias Schwalb, Philipp Graf, Michael Hübner, Jürgen Becker, Enno Lübbers, Marco Platzner
Fine grain reconfigurable architectures. 348 - Sven Eisenhardt, Thomas Schweizer, Julio A. de Oliveira Filho, Tobias Oppold, Wolfgang Rosenstiel, Alexander Thomas, Jürgen Becker, Frank Hannig
Coarse-grained reconfiguration. 349 - Heiko Hinkelmann, Peter Zipf
Application-specific reconfigurable processors. 350 - Andreas Schallenberg, Achim Rettberg, Wolfgang Nebel, Franz-Josef Rammig:
Seamless design flow for reconfigurable systems. 351 - Thilo Pionteck
Network processors. 352 - Sebastian Lange, Martin Middendorf:
Hyperreconfigurable architectures. 353
Synthesis
- Martin Langhammer:
Floating point datapath synthesis for FPGAs. 355-360 - Karel Bruneel, Dirk Stroobandt:
Automatic generation of run-time parameterizable configurations. 361-366 - Miguel Lino Silva, João Canas Ferreira
Generation of partial FPGA configurations at run-time. 367-372
Algorithm Acceleration
- Changjian Gao, Shih-Lien Lu:
Novel FPGA based Haar classifier face detection algorithm acceleration. 373-378 - David Boland
An FPGA-based implementation of the MINRES algorithm. 379-384 - Markos Papadonikolakis, Christos-Savvas Bouganis
Efficient FPGA mapping of Gilbert's algorithm for SVM training on large-scale classification problems. 385-390
Optimization
- Christophe Wolinski, Krzysztof Kuchcinski
Area and reconfiguration time minimization of the communication network in regular 2D reconfigurable architectures. 391-396 - Stanislaw Deniziak
An symbolic decomposition of functions with multi-valued inputs and outputs for FPGA-based implementation. 397-402 - Hagen Gädke, Florian Stock, Andreas Koch:
Memory access parallelisation in high-level language compilation for reconfigurable adaptive computers. 403-408
Surveys and Trends
- Claudio Brunelli, Fabio Garzia, Jari Nurmi
Reconfigurable hardware: The holy grail of matching performance with programming productivity. 409-414 - Edward A. Stott, N. Pete Sedcole, Peter Y. K. Cheung:
Fault tolerant methods for reliability in FPGAs. 415-420 - Yoann Guillemenet, Lionel Torres, Gilles Sassatelli, Nicolas Bruchon, Ilham Hassoune:
A non-volatile run-time FPGA using thermally assisted switching MRAMS. 421-426
Reconfigurable Architectures
- Ping Chen, Andy Ye:
The effect of sparse switch patterns on the area efficiency of multi-bit routing resources in field-programmable gate arrays. 427-430 - Kimon Karras, Elias S. Manolakos
An embedded dynamically self-reconfigurable Master-Slaves MPSoC architecture. 431-434 - Oliver A. Pfänder, Hans-Jörg Pfleiderer:
EMMA - A suggestion for an embedded multi-precision multiplier array for FPGAs. 435-438 - Immacolata Colacicco, Giacomo Marchiori, Raffaele Tripiccione
The hardware application platform of the hartes project. 439-442
Design Methods and Tools
- Eoin Creedon, Michael Manzke
Scalable high performance computing on FPGA clusters using message passing. 443-446 - Haile Yu, Yuk Hei Chan, Philip Heng Wai Leong
FPGA interconnect design using logical effort. 447-450 - Jason Wu, John Williams
An ILP formulation for architectural synthesis and application mapping on FPGA-based hybrid multi-processor SOC. 451-454 - Marco D. Santambrogio
Operating system support for online partial dynamic reconfiguration management. 455-458 - Meikang Qiu, Jiande Wu, Chun Jason Xue
Loop scheduling and assignment to minimize energy while hiding latency for heterogeneous multi-bank memory. 459-462 - Shinobu Nagayama, Tsutomu Sasao, Jon T. Butler:
Numerical function generators using bilinear interpolation. 463-466
Applications
- Roberto Perez-Andrade, René Cumplido, Claudia Feregrino Uribe, Fernando Martin del Campo:
A versatile hardware architecture for a CFAR detector based on a linear insertion sorter. 467-470 - Amit Pande, Joseph Zambreno:
Polymorphic wavelet architectures using reconfigurable hardware. 471-474 - Chiu-Wah Ng, Ngai Wong, Hayden Kwok-Hay So
Direct sigma-delta modulated signal processing in FPGA. 475-478 - Andre Guntoro
A lifting-based DWT and IDWT processor with multi-context configuration and normalization factor. 479-482
Reconfigurable Architectures
- Jim Harkin
Reconfigurable platforms and the challenges for large-scale implementations of spiking neural networks. 483-486 - Claudio Brunelli, Fabio Garzia, Carmelo Giliberto, Jari Nurmi
A dedicated DMA logic addressing a time multiplexed memory to reduce the effects of the system bus bottleneck. 487-490 - Hongbing Fan, Jason Ernst, Yu-Liang Wu:
Customized Reconfigurable Interconnection Networks for multiple application SOCS. 491-494 - Diana Göhringer, Michael Hübner, Thomas Perschke, Jürgen Becker:
New dimensions for multiprocessor architectures: Ondemand heterogeneity, infrastructure and performance through reconfigurability - the RAMPSoC approach. 495-498
Design Methods and Tools
- Yasuhiro Ito, Yutaka Sugawara, Mary Inaba, Kei Hiraki:
CVC: The C to RTL compiler for callback-based verification model. 499-502 - Yuuri Sugihara, Yohei Kume, Kazutoshi Kobayashi, Hidetoshi Onodera:
Performance optimization by track swapping on critical paths utilizing random variations for FPGAS. 503-506 - Kenshu Seto, Yuta Nonaka, Takuya Maruizumi, Yasuhiro Shiraki:
SAT-based resource binding for reducing critical path delays. 507-510 - Ralf Joost, Ralf Salomon:
BOUNCE, a new approach to measure sub-nanosecond time intervals. 511-514 - Stephen McKeown
Power efficient DSP datapath configuration methodology for FPGA. 515-518
Applications
- Ahmad Sghaier, Shawki Areibi, Robert D. Dony:
IEEE802.16-2004 OFDM functions implementation on FPGAS with design exploration. 519-522 - Séamas McGettrick, Dermot Geraghty, Ciarán McElroy:
An FPGA architecture for the Pagerank eigenvector problem. 523-526 - Alexander Danilin, Sergei Sawitzki, Erik Rijshouwer:
Reconfigurable cell architecture for multi-standard interleaving and deinterleaving in digital communication systems. 527-530 - Mamoun F. Al-Mistarihi:
Separable implementation of the second order Volterra filter (SOVF) in Xilinx Virtex-E FPGA. 531-534
Reconfigurable Architectures
- Christopher Claus, Bin Zhang, Walter Stechele, Lars Braun, Michael Hübner, Jürgen Becker:
A multi-platform controller allowing for maximum Dynamic Partial Reconfiguration throughput. 535-538 - Almudena Lindoso
Coarse-grain dynamically reconfigurable coprocessor for image processing in SOPC. 539-542 - Kazuya Tanigawa, Tetsuya Zuyama, Takuro Uchida, Tetsuo Hironaka:
Exploring compact design on high throughput coarse grained reconfigurable architectures. 543-546 - Izhar Zaidi, Atukem Nabina, Cedric Nishan Canagarajah, José L. Núñez-Yáñez
Evaluating dynamic partial reconfiguration in the integer pipeline of a FPGA-based opensource processor. 547-550
Design Methods and Tools
- Christian Hochberger, Alexander Weiss:
A new methodology for debugging and validation of soft cores. 551-554 - Diego Puschini, Fabien Clermidy, Pascal Benoit, Gilles Sassatelli, Lionel Torres:
Convergence analysis of run-time distributed optimization on adaptive systems using game theory. 555-558 - Xing Wei, Juanjuan Chen
MacroMap: A technology mapping algorithm for heterogeneous FPGAs with effective area estimation. 559-562 - Norbert Abel, Frederik Grüll, Nick Meier, Andreas Beyer, Udo Kebschull:
Parallel hardware objects for dynamically partial reconfiguration. 563-566 - Hayden Kwok-Hay So
File system access from reconfigurable FPGA hardware processes in BORPH. 567-570 - Enrique Cantó
Self-recofigurable embedded systems on Spartan-3. 571-574
Applications
- Jing Hu, Steven F. Quigley, Andrew Chan
An element-by-element preconditioned Conjugate Gradient solver of 3D tetrahedral finite elements on an FPGA coprocessor. 575-578 - James W. Crouch, Hiren J. Patel, Yong C. Kim, Robert W. Bennington:
Creating unique identifiers on field programmable gate arrays using natural processing variations. 579-582 - Haiting Tian, Shakith Fernando, Hock Wei Soon, Yajun Ha, Nanguang Chen:
Design of a high speed pseudo-random bit sequence based time resolved single photon counter on FPGA. 583-586
Reconfigurable Architectures
- Christopher Claus, Walter Stechele, Matthias Kovatsch, Josef Angermeier, Jürgen Teich:
A comparison of embedded reconfigurable video-processing architectures. 587-590 - Syed Waqar Nabi
Interface and Reconfiguration Controller for a wireless MAC-oriented dynamically reconfigurable hardware co-processor. 591-594 - César Pedraza, Emilio Castillo
Cluster architecture based on low cost reconfigurable hardware. 595-598 - Andreas Ehliar, Per Karlström, Dake Liu:
A high performance microprocessor with DSP extensions optimized for the Virtex-4 FPGA. 599-602
Design Methods and Tools
- Kevin K. Liu, Charles B. Cameron, Antal A. Sarkady:
Comparing throughput and power consumption in both sequential and reconfigurable processors. 603-606 - Lars Braun, Katarina Paulsson, Herrmann Krömer, Michael Hübner, Jürgen Becker:
Data path driven waveform-like reconfiguration. 607-610 - Wenyin Fu, Katherine Compton:
Active kernel monitoring to combat scheduler gaming in reconfigurable computing systems. 611-614 - Hanyu Liu, Xiaolei Chen, Yajun Ha:
An architecture and timing-driven routing algorithm for area-efficient FPGAs with time-multiplexed interconnects. 615-618 - Markus Koester, Wayne Luk, Geoffrey Brown:
A hardware compilation flow for instance-specific VLIW cores. 619-622
Applications
- Michail Zampetakis, Vasilis Samoladas, Apostolos Dollas:
A reconfigurable accelerator for quantum computations. 623-626 - Andre Guntoro
High-performance fpga-based floating-point adder with three inputs. 627-630 - Panagiotis Afratis, Euripides Sotiriades, Grigorios Chrysos, Sotiria Fytraki, Dionisios N. Pnevmatikatos
A rate-based prefiltering approach to blast acceleration. 631-634 - Diego Pedro Morales
Enhancing ADC resolution through Field Programmable Analog Array dynamic reconfiguration. 635-638 - George Kornaros
Architecture and implementation of a Frame Aggregation Unit for optical frame-based switching. 639-642
Reconfigurable Architectures
- Fujie Wong, Yajun Ha:
A low overhead fault tolerant FPGA with new connection box. 643-646
Design Methods and Tools
- Sayaka Shida, Yuichiro Shibata, Kiyoshi Oguri, Duncan A. Buell
An optimization method of DMA transfer for a general purpose reconfigurable machine. 647-650 - Vlad Mihai Sima
Resource allocation algorithm and OpenMP extensions for parallel execution on a heterogeneous reconfigurable platform. 651-654 - Betul Buyukkurt, Walid A. Najjar
Compiler generated systolic arrays for wavefront algorithm acceleration on FPGAs. 655-658 - Shilpa Bhoj, Dinesh Bhatia
A dynamic temperature control simulation system for FPGAs. 659-662
Applications
- Masato Yoshimi, Yuri Nishikawa
Practical implementation of a network-based stochastic biochemical simulation system on an FPGA. 663-666 - Jason R. Villarreal, Walid A. Najjar
Compiled hardware acceleration of Molecular Dynamics code. 667-670 - Gang Zhou, Li Li, Harald Michalik:
Area optimization of bit parallel finite field multipliers with fast carry logic on FPGAS. 671-674 - Tim Güneysu
Enhancing COPACOBANA for advanced applications in cryptography and cryptanalysis. 675-678 - Donald G. Bailey
Connected components analysis of streamed images. 679-682
Surveys, Trends and Education
- Thilo Pionteck
On the design parameters of runtime reconfigurable systems. 683-686 - Yamuna Rajasekhar, William V. Kritikos, Andrew G. Schmidt, Ron Sass:
Teaching FPGA system design via a remote laboratory facility. 687-690 - Tobias Becker
Towards benchmarking energy efficiency of reconfigurable architectures. 691-694
PhD Forum Presentations
- Haile Yu:
FPGA interconnect sizing using extended logical effort model. 695-696 - Nicolas Saint-Jean, Gilles Sassatelli, Pascal Benoit, Lionel Torres, Michel Robert:
Bio-inspiration helps computers: A new machine. 697-698 - Katarina Paulsson, Michael Hübner, Jürgen Becker:
Exploitation of dynamic and partial hardware reconfiguration for on-line power/performance optimization. 699-700 - Shilpa Bhoj:
Thermal aware FPGA architectures and CAD. 701-702 - Justin S. J. Wong
Combating process variation on FPGAS with a precise at-speed delay measurement method. 703-704 - Gary Chun Tak Chow:
Adaptive precision technique for genetic algorithms. 705-706 - Heiner Giefers
Reconfigurable many-cores with lean interconnect. 707-708
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
last updated on 2024-12-22 18:47 CET by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by: