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Mateus B. Rutzig
Mateus Beck Rutzig
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2020 – today
- 2024
- [c55]Julio Costella Vicenzi, Guilherme Korol, Michael Guilherme Jordan, Mateus Beck Rutzig, Antonio Carlos Schneider Beck:
Exploiting Virtual Layers and Pruning for FPGA-Based Adaptive Traffic Classification. DSD 2024: 194-201 - [c54]Julio Costella Vicenzi, Michael Guilherme Jordan, Guilherme Korol, Tiago Knorst, Mateus Beck Rutzig, Antonio Carlos Schneider Beck:
TARA: Enhancing Real-Time Network Traffic Classification with Hardware Virtual Layers. SBCCI 2024: 1-5 - [c53]Tiago Knorst, Michael Guilherme Jordan, Guilherme Korol, Mateus Beck Rutzig, Antonio Carlos Schneider Beck:
An Automatic Framework for Collaborative CPU Thread Throttling and FPGA HLS-Versioning. SBESC 2024: 1-6 - [c52]Lucas Rister Machado, Michael Guilherme Jordan, Antonio Carlos Schneider Beck, Mateus Beck Rutzig:
Exploration Tool for Collaborative Provisioning and DVFS in Heterogeneous Cloud Environments. SBESC 2024: 1-6 - 2023
- [j14]Michael Guilherme Jordan, Julio Costella Vicenzi, Tiago Knorst, Guilherme Korol, Antonio Carlos Schneider Beck, Mateus Beck Rutzig:
Multiprovision: a Design Space Exploration tool for multi-tenant resource provisioning in CPU-GPU environments. Des. Autom. Embed. Syst. 27(4): 241-273 (2023) - [j13]Michael Guilherme Jordan
, Bernardo Neuhaus Lignati, Guilherme Korol
MVSym: Efficient symbiotic exploitation of HLS-kernel multi-versioning for collaborative CPU-FPGA cloud systems. Integr. 93: 102052 (2023) - [j12]Michael Guilherme Jordan, Guilherme Korol, Tiago Knorst, Mateus Beck Rutzig, Antonio Carlos Schneider Beck:
Energy-aware fully-adaptive resource provisioning in collaborative CPU-FPGA cloud environments. J. Parallel Distributed Comput. 176: 55-69 (2023) - [c51]Julio Costella Vicenzi
Adaptive Inference on Reconfigurable SmartNICs for Traffic Classification. AINA (2) 2023: 137-148 - [c50]Guilherme Korol, Michael Guilherme Jordan, Mateus Beck Rutzig, Jerónimo Castrillón, Antonio Carlos Schneider Beck:
Pruning and Early-Exit Co-Optimization for CNN Acceleration on FPGAs. DATE 2023: 1-6 - [c49]Michael Guilherme Jordan, Guilherme Korol, Tiago Knorst, Mateus Beck Rutzig, Antonio Carlos Schneider Beck:
Resource Provisioning for CPU-FPGA Environments with Adaptive HLS-Versioning and DVFS. ISVLSI 2023: 1-6 - [c48]Guilherme Korol, Michael Guilherme Jordan, Mateus Beck Rutzig, Jerónimo Castrillón, Antonio Carlos Schneider Beck:
Design Space Exploration for CNN Offloading to FPGAs at the Edge. ISVLSI 2023: 1-6 - [c47]Julio Costella Vicenzi, Guilherme Korol, Michael Guilherme Jordan, Wagner Ourique de Morais, Hazem Ali
Dynamic Offloading for Improved Performance and Energy Efficiency in Heterogeneous IoT-Edge-Cloud Continuum. ISVLSI 2023: 1-6 - 2022
- [j11]Tiago Knorst
An energy efficient multi-target binary translator for instruction and data level parallelism exploitation. Des. Autom. Embed. Syst. 26(1): 55-82 (2022) - [j10]Michael Guilherme Jordan
ERIN: Energy-Aware Resource-Provisioning Framework for CPU-FPGA Multitenant Environment. IEEE Des. Test 39(6): 138-146 (2022) - [c46]Guilherme Korol, Michael Guilherme Jordan, Mateus Beck Rutzig, Antonio Carlos Schneider Beck:
AdaFlow: A Framework for Adaptive Dataflow CNN Acceleration on FPGAs. DATE 2022: 244-249 - [c45]Guilherme Korol, Michael Guilherme Jordan, Mateus Beck Rutzig, Antonio Carlos Schneider Beck:
ConfAx: Exploiting Approximate Computing for Configurable FPGA CNN Acceleration at the Edge. ISCAS 2022: 1650-1654 - [c44]Tiago Knorst, Guilherme Korol, Michael Guilherme Jordan, Julio Costella Vicenzi, Arthur Francisco Lorenzon, Mateus Beck Rutzig, Antonio Carlos Schneider Beck:
On the benefits of Collaborative Thread Throttling and HLS-Versioning in CPU-FPGA Environments. SBCCI 2022: 1-6 - [c43]Cesar Tadeu Pozzer, João B. Martins, Lisandra M. Fontoura, Luís A. Lima Silva, Mateus B. Rutzig, Raul Ceretta Nunes, Edison Pignaton de Freitas:
SIS-ASTROS: An Integrated Simulation System for the Artillery Saturation Rocket System (ASTROS). SIMULTECH 2022: 194-201 - 2021
- [j9]Janaina Schwarzrock
Dynamic concurrency throttling on NUMA systems and data migration impacts. Des. Autom. Embed. Syst. 25(2): 135-160 (2021) - [j8]Michael Guilherme Jordan
Resource-Aware Collaborative Allocation for CPU-FPGA Cloud Environments. IEEE Trans. Circuits Syst. II Express Briefs 68(5): 1655-1659 (2021) - [j7]Guilherme Korol, Michael Guilherme Jordan, Mateus Beck Rutzig, Antonio Carlos Schneider Beck:
Synergistically Exploiting CNN Pruning and HLS Versioning for Adaptive Inference on Multi-FPGAs at the Edge. ACM Trans. Embed. Comput. Syst. 20(5s): 59:1-59:26 (2021) - [c42]Bernardo Neuhaus Lignati, Michael Guilherme Jordan, Guilherme Korol, Mateus Beck Rutzig, Antonio Carlos Schneider Beck:
Exploiting HLS-Generated Multi-Version Kernels to Improve CPU-FPGA Cloud Systems. ASP-DAC 2021: 536-541 - [c41]Michael Guilherme Jordan, Guilherme Korol, Mateus Beck Rutzig, Antonio Carlos Schneider Beck:
FAIR: Fully-Adaptive Framework for Improving Resource Provisioning in Collaborative CPU-FPGA Cloud Environments. SBAC-PAD 2021: 147-156 - [c40]Tiago Knorst, Michael Guilherme Jordan, Arthur Francisco Lorenzon, Mateus Beck Rutzig, Antonio Carlos Schneider Beck:
ETCF - Energy-Aware CPU Thread Throttling and Workload Balancing Framework for CPU-FPGA Collaborative Environments. SBESC 2021: 1-8 - [c39]Julio Costella Vicenzi
TRIPP: Transparent Resource Provisioning for Multi-Tenant CPU-GPU based Cloud Environments. SBESC 2021: 1-8 - 2020
- [j6]Michael Guilherme Jordan
Data clustering for efficient approximate computing. Des. Autom. Embed. Syst. 24(1): 3-22 (2020) - [c38]Guilherme Korol, Michael Guilherme Jordan, Marcelo Brandalero, Michael Hübner, Mateus Beck Rutzig, Antonio Carlos Schneider Beck:
MCEA: A Resource-Aware Multicore CGRA Architecture for the Edge. FPL 2020: 33-39 - [c37]Rafael Follmann Faccenda
Maximizing Throughput-per-Joule of a Hybrid Communication Infrastructure Through a Software-Hardware based DVFS Mechanism. SBCCI 2020: 1-6 - [c36]Tiago Knorst, Julio Costella Vicenzi
Unlocking the Full Potential of Heterogeneous Accelerators by Using a Hybrid Multi-Target Binary Translator. SBCCI 2020: 1-6 - [c35]Raul Silveira Silva, Guilherme Korol, Michael Guilherme Jordan, Marcelo Brandalero, Michael Hübner, Monica Magalhães Pereira, Mateus Beck Rutzig, Antonio Carlos Schneider Beck:
A Management Technique for Concurrent Access to a Reconfigurable Accelerator. SBCCI 2020: 1-6
2010 – 2019
- 2019
- [c34]Michael Guilherme Jordan, Tiago Knorst, Julio Costella Vicenzi
Boosting SIMD Benefits through a Run-time and Energy Efficient DLP Detection. DATE 2019: 722-727 - [c33]Guilherme Korol, Michael Guilherme Jordan, Marcelo Brandalero, Mateus Beck Rutzig, Antonio Carlos Schneider Beck:
Power-Aware Phase Oriented Reconfigurable Architecture. ICECS 2019: 626-629 - [c32]Guilherme Korol, Michael Guilherme Jordan, Raul Silveira Silva, Monica Magalhães Pereira, Marcelo Brandalero, Mateus Beck Rutzig, Antonio Carlos Schneider Beck:
A Runtime Power-Aware Phase Predictor for CGRAs. ReConFig 2019: 1-8 - 2018
- [c31]Rafael Fão de Moura, Michael Guilherme Jordan, Antonio Carlos Schneider Beck, Mateus Beck Rutzig
Exploiting Partial Reconfiguration on a Dynamic Coarse Grained Reconfigurable Architecture. ARC 2018: 355-366 - [c30]Jeckson Dellagostin Souza
DIM-VEX: Exploiting Design Time Configurability and Runtime Reconfigurability. ARC 2018: 367-378 - [c29]Michael Guilherme Jordan, Tiago Knorst, Mateus Beck Rutzig
Improving Software Productivity and Performance Through a Transparent SIMD Execution. SBCCI 2018: 1-6 - [c28]Michael Guilherme Jordan, Tiago Knorst, Julio Costella Vicenzi
Runtime Vectorization of Conditional Code and Dynamic Range Loops to ARM NEON Engine. SBESC 2018: 67-74 - [c27]Rafael Follmann Faccenda
HyHeMPS: A Hybrid Communication Infrastructure for MPSoCs. SBESC 2018: 231-236 - [c26]Juliana Rubenich Brondani, Luís A. Lima Silva, Mateus B. Rutzig, Cesar Tadeu Pozzer, Raul Ceretta Nunes, João B. Martins, Edison Pignaton de Freitas
Semi-Autonomous Navigation for Virtual Tactical Simulations in the Military Domain. SIMULTECH 2018: 443-450 - 2017
- [c25]Wagner dos Santos Marques, Paulo Silas Severo de Souza, Arthur Francisco Lorenzon, Antonio Carlos Schneider Beck, Mateus Beck Rutzig
Improving EDP in multi-core embedded systems through multidimensional frequency scaling. ISCAS 2017: 1-4 - [c24]Josimar Sfreddo, Rafael Fao de Moura, Michael Guilherme Jordan, Jeckson Dellagostin Souza, Antonio Carlos Schneider Beck, Mateus Beck Rutzig
A framework to automatically generate heterogeneous organization reconfigurable multiprocessing. ISCAS 2017: 1-4 - 2016
- [c23]Jeckson Dellagostin Souza, João Victor Gomes Cachola, Luigi Carro, Mateus Beck Rutzig
Evaluating Schedulers in a Reconfigurable Multicore Heterogeneous System. ARC 2016: 261-272 - [c22]Jeckson Dellagostin Souza, Luigi Carro, Mateus Beck Rutzig, Antonio Carlos Schneider Beck:
A reconfigurable heterogeneous multicore with a homogeneous ISA. DATE 2016: 1598-1603 - [c21]Rafael Fao de Moura, Jeckson Dellagostin Souza, Luigi Carro, Antonio Carlos Schneider Beck, Mateus Beck Rutzig
The Impact of Heterogeneity on a Reconfigurable Multicore System. ISVLSI 2016: 701-706 - 2015
- [j5]Mateus Beck Rutzig
Adaptive and dynamic reconfigurable multiprocessor system to improve software productivity. IET Comput. Digit. Tech. 9(1): 63-72 (2015) - [c20]Thiago Baldissera Biazus, Mateus Beck Rutzig
Reducing Storage Costs of Reconfiguration Contexts by Sharing Instruction Memory Cache Blocks. ARC 2015: 3-14 - 2014
- [j4]Antonio Carlos Schneider Beck, Mateus Beck Rutzig
A transparent and adaptive reconfigurable system. Microprocess. Microsystems 38(5): 509-524 (2014) - [c19]Jeckson Dellagostin Souza, Luigi Carro, Mateus Beck Rutzig
Towards a Dynamic and Reconfigurable Multicore Heterogeneous System. SBESC 2014: 73-78 - 2013
- [j3]Jair Fajardo Junior, Mateus B. Rutzig
Towards a multiple-ISA embedded system. J. Syst. Archit. 59(2): 103-119 (2013) - [c18]Mateus B. Rutzig, Antonio Carlos Schneider Beck, Luigi Carro:
A transparent and energy aware reconfigurable multiprocessor platform for simultaneous ILP and TLP exploitation. DATE 2013: 1559-1564 - [c17]Mateus Beck Rutzig
A run-time adaptive multiprocessor system. ISCAS 2013: 1664-1667 - [p2]Luigi Carro, Mateus Beck Rutzig
Multicore Systems on Chip. Handbook of Signal Processing Systems 2013: 517-551 - 2012
- [j2]Mateus B. Rutzig
Mixing static and dynamic strategies for high performance and low area reconfigurable systems. Int. J. High Perform. Syst. Archit. 4(1): 13-24 (2012) - [c16]Fakhar Anjam, Stephan Wong, Luigi Carro
Simultaneous reconfiguration of issue-width and instruction cache for a VLIW processor. ICSAMOS 2012: 183-192 - 2011
- [j1]Mateus B. Rutzig
Boosting Parallel Applications Performance on Applying DIM Technique in a Multiprocessing Environment. Int. J. Reconfigurable Comput. 2011: 546962:1-546962:13 (2011) - [c15]Mateus B. Rutzig
CReAMS: An Embedded Multiprocessor Platform. ARC 2011: 118-124 - [c14]Jair Fajardo Junior, Mateus B. Rutzig
Towards an Adaptable Multiple-ISA Reconfigurable Processor. ARC 2011: 157-168 - [c13]Alexandre A. Junqueira, Mateus B. Rutzig
A reconfigurable fabric supporting full C/C++ input. ReCoSoC 2011: 1-6 - 2010
- [c12]Thiago Lo, Antonio Carlos Schneider Beck, Mateus B. Rutzig
A low-energy approach for context memory in reconfigurable systems. IPDPS Workshops 2010: 1-8 - [c11]Mateus B. Rutzig
TLP and ILP exploitation through a reconfigurable multiprocessor system. IPDPS Workshops 2010: 1-8 - [p1]Luigi Carro, Mateus Beck Rutzig:
Multi-core Systems on Chip. Handbook of Signal Processing Systems 2010: 485-514
2000 – 2009
- 2009
- [c10]Mateus B. Rutzig
Dynamically Adapted Low Power ASIPs. ARC 2009: 110-122 - [c9]Ricardo S. Ferreira, Marcone Laure, Antonio Carlos Schneider Beck, Thiago Lo, Mateus B. Rutzig
A low cost and adaptable routing network for reconfigurable systems. IPDPS 2009: 1-8 - 2008
- [c8]Antonio Carlos Schneider Beck, Mateus B. Rutzig
Run-time Adaptable Architectures for Heterogeneous Behavior Embedded Systems. ARC 2008: 111-123 - [c7]Antonio Carlos Schneider Beck, Mateus B. Rutzig
Transparent Reconfigurable Acceleration for Heterogeneous Embedded Applications. DATE 2008: 1208-1213 - [c6]Ricardo S. Ferreira, Marcone Laure, Mateus B. Rutzig
Reducing interconnection cost in coarse-grained dynamic computing through multistage network. FPL 2008: 47-52 - [c5]Mateus B. Rutzig
Balancing reconfigurable data path resources according to application requirements. IPDPS 2008: 1-8 - [c4]Eduardo Luis Rhod, Mateus B. Rutzig
Binary translation process to optimize nanowire arrays usage. ISCAS 2008: 396-399 - 2007
- [c3]Mateus B. Rutzig, Antonio Carlos Schneider Beck, Luigi Carro
Transparent Dataflow Execution for Embedded Applications. ISVLSI 2007: 47-54 - 2006
- [c2]Antonio Carlos Schneider Beck, Mateus B. Rutzig, Luigi Carro:
Advantages of Java Processors in Cache Performance and Power for Embedded Applications. SAMOS 2006: 321-330 - [c1]Antonio Carlos Schneider Beck, Mateus B. Rutzig, Luigi Carro:
Cache performance impacts for stack machines in embedded systems. SBCCI 2006: 155-160
Coauthor Index
[c55] [c54] [c53] [c52] [j14] [j13] [j12] [c51] [c50] [c49] [c48] [c47] [j11] [j10] [c46] [c45] [c44] [j9] [j8] [j7] [c42] [c41] [c40] [c39] [j6] [c38] [c37] [c36] [c35] [c33] [c32] [c31] [c30] [c25] [c24] [c23] [c22] [c21] [j5] [j4] [c19] [j3] [c18] [c17] [j2] [j1] [c15] [c14] [c12] [c11] [c10] [c9] [c8] [c7] [c6] [c5] [c3] [c2] [c1]
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last updated on 2024-12-19 22:13 CET by the dblp team
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