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Kenshu Seto
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2020 – today
- 2021
- [c12]Kenshu Seto:
Scalar replacement in the presence of multiple write accesses for high-level synthesis. DATE 2021: 26-31 - 2020
- [j11]Kenshu Seto:
Shift Register Initialization in Scalar Replacement for Reducing Code Size. IPSJ Trans. Syst. LSI Des. Methodol. 13: 2-9 (2020)
2010 – 2019
- 2019
- [j10]Kenshu Seto:
Scalar Replacement with Circular Buffers. IPSJ Trans. Syst. LSI Des. Methodol. 12: 13-21 (2019) - [c11]Kenshu Seto, Hamid Nejatollahi
, Jiyoung An, Sujin Kang, Nikil D. Dutt
Small Memory Footprint Neural Network Accelerators. ISQED 2019: 253-258 - 2018
- [j9]Kenshu Seto:
Scalar Replacement with Polyhedral Model. IPSJ Trans. Syst. LSI Des. Methodol. 11: 46-56 (2018) - 2014
- [j8]Shingo Kusakabe, Kenshu Seto:
Forwarding Unit Generation for Loop Pipelining in High-level Synthesis. Inf. Media Technol. 9(4): 413-418 (2014) - [j7]Shingo Kusakabe, Kenshu Seto:
Forwarding Unit Generation for Loop Pipelining in High-level Synthesis. IPSJ Trans. Syst. LSI Des. Methodol. 7: 119-124 (2014) - 2013
- [j6]Yuta Kato, Kenshu Seto:
Loop Fusion with Outer Loop Shifting for High-level Synthesis. Inf. Media Technol. 8(2): 306-310 (2013) - [j5]Yuta Kato, Kenshu Seto:
Loop Fusion with Outer Loop Shifting for High-level Synthesis. IPSJ Trans. Syst. LSI Des. Methodol. 6: 71-75 (2013) - 2010
- [j4]Kenshu Seto, Masahiro Fujita:
Custom Instruction Generation for Configurable Processors with Limited Numbers of Operands. Inf. Media Technol. 5(2): 376-387 (2010) - [j3]Kenshu Seto, Masahiro Fujita:
Custom Instruction Generation for Configurable Processors with Limited Numbers of Operands. IPSJ Trans. Syst. LSI Des. Methodol. 3: 57-68 (2010)
2000 – 2009
- 2009
- [j2]Shanghua Gao, Hiroaki Yoshida, Kenshu Seto, Satoshi Komatsu, Masahiro Fujita:
Interconnect-Aware Pipeline Synthesis for Array-Based Architectures. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 92-A(6): 1464-1475 (2009) - 2008
- [j1]Masahiro Fujita, Kenshu Seto, Thanyapat Sakunkonchak:
Dependence Graph Based Verification and Synthesis of Hardware/Software Co-Designs with SAT Related Formulation. J. Satisf. Boolean Model. Comput. 5(1-4): 57-82 (2008) - [c10]Kenshu Seto, Yuta Nonaka, Takuya Maruizumi, Yasuhiro Shiraki:
SAT-based resource binding for reducing critical path delays. FPL 2008: 507-510 - [c9]Kenshu Seto, Masahiro Fujita:
Custom Instruction Generation with High-Level Synthesis. SASP 2008: 14-19 - 2007
- [c8]Shigeru Watanabe, Kenshu Seto, Yuji Ishikawa, Satoshi Komatsu, Masahiro Fujita:
Protocol Transducer Synthesis using Divide and Conquer approach. ASP-DAC 2007: 280-285 - [c7]Shanghua Gao, Kenshu Seto, Satoshi Komatsu, Masahiro Fujita:
Interconnect-aware Pipeline Synthesis for Array based Reconfigurable Architectures. IESS 2007: 121-134 - 2006
- [c6]Shota Watanabe, Yuji Ishikawa, Kenshu Seto, Satoshi Komatsu, Masahiro Fujita:
Dynamically reconfigurable protocol transducer. FPT 2006: 341-344 - 2005
- [c5]Shanghua Gao, Kenshu Seto, Satoshi Komatsu, Masahiro Fujita:
Pipeline Scheduling for Array Based Reconfigurable Architectures Considering Interconnect Delays. FPT 2005: 137-144 - 2003
- [c4]Masahiro Fujita, Satoshi Komatsu, Hiroshi Saito, Kenshu Seto, Thanyapat Sakunkonchak, Yoshihisa Kojima:
Field Modifiable Architecture with FPGAs and its Design/Verification/Debugging Methodologies. HICSS 2003: 279 - [c3]Hiroshi Saito, Kenshu Seto, Yoshihisa Kojima, Satoshi Komatsu, Masahiro Fujita:
Engineering Changes in Field Modifiable Architectures. MEMOCODE 2003: 87-94 - 2002
- [c2]Satoshi Komatsu, Yoshihisa Kojima, Hiroshi Saito, Kenshu Seto, Masahiro Fujita:
Field modifiable architecture with FPGAs and its design methodology. FPT 2002: 382-385 - [c1]Yoshihisa Kojima, Hiroshi Saito, Kenshu Seto, Satoshi Komatsu, Masahiro Fujita:
Field Modifiable Architecture and its Design Methodology: System Design Without Logic Synthesis. IWLS 2002: 103-108
Coauthor Index
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