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CICC 2022: Newport Beach, CA, USA
- IEEE Custom Integrated Circuits Conference, CICC 2022, Newport Beach, CA, USA, April 24-27, 2022. IEEE 2022, ISBN 978-1-6654-0756-4
- Jie Zhou, Huizhen Jenny Qian, Bingzheng Yang, Yiyang Shu, Xun Luo:
A Phase-Modulation Phase-Shifting Phased-Array Transmitter with 10-Bit Fast-Locking Phase Self-Calibration and 0/2.5/6/12dB Power Back-Offs Efficiency Enhancement. 1-2 - Jennifer Hasler:
The Rise of SoC FPAA Devices. 1-8 - Zhaoqing Wang
, Sung Justin Kim, Keith A. Bowman, Mingoo Seok:
Review, Survey, and Benchmark of Recent Digital LDO Voltage Regulators. 1-8 - Siavash Kananian, Cheng Chen, Ada S. Y. Poon:
An energy-harvesting stamp-sized reader for distance-immune interrogation of passive wireless sensors. 1-2 - Bingzheng Yang, Huizhen Jenny Qian, Yiyang Shu, Jie Zhou, Xun Luo:
Watt-Level Triple-Mode Quadrature SFCPA with 56 Peaks for Ultra-Deep PBO Efficiency Enhancement Using IQ Intrinsic Interaction and Adaptive Phase Compensation. 1-2 - Bingzheng Yang, Huizhen Jenny Qian, Yiyang Shu, Jie Zhou, Xun Luo:
22-30GHz Quadrature Hybrid SCPA with LO Leakage Self-Suppression and Distributed Parasitic-Cancelling Sub-PA Array for Linearity and Efficiency Enhancement. 1-2 - Zhiyong Li
An 0.92 mJ/frame High-quality FHD Super-resolution Mobile Accelerator SoC with Hybrid-precision and Energy-efficient Cache. 1-2 - Rozhan Rabbani
A $36\times 40$ Wireless Fluorescence Image Sensor for Real-Time Microscopy in Cancer Therapy. 1-2 - Liheng Liu, Tianxiang Qu
A 0.8V/0.6V 2.2μW Time-Domain Analog Front-End with $540\text{mV}_{\text{pp}}$ Input Range, 81.6dB SNDR and $80\mathrm{M}\Omega$ Input Impedance. 1-2 - Bo Zhang, Jyotishman Saikia, Jian Meng, Dewei Wang, Soonwan Kwon, Sungmeen Myung
A 177 TOPS/W, Capacitor-based In-Memory Computing SRAM Macro with Stepwise-Charging/Discharging DACs and Sparsity-Optimized Bitcells for 4-Bit Deep Convolutional Neural Networks. 1-2 - Tania Moeinfard, Georg Zoidl, Hossein Kassiri:
A SAR-Assisted DC-Coupled Chopper-Stabilized 20μs-Artifact-Recovery $\Delta \Sigma$ ADC for Simultaneous Neural Recording and Stimulation. 1-2 - Arindam Basu
Spiking Neural Network Integrated Circuits: A Review of Trends and Future Directions. 1-8 - Taejoong Song, Hakchul Jung, Giyoung Yang
3nm Gate-All-Around (GAA) Design-Technology Co-Optimization (DTCO) for succeeding PPA by Technology. 1-7 - Yuanming Zhu
A 38GS/s 7b Time-Interleaved Pipelined-SAR ADC with Speed-Enhanced Bootstrapped Switch in 22nm FinFET. 1-2 - Animesh Gupta, Viveka Konandur Rajanna, Thoithoi Salam, Saurabh Jain, Orazio Aiello, Paolo Crovetti, Massimo Alioto:
DDPMnet: All-Digital Pulse Density-Based DNN Architecture with 228 Gate Equivalents/MAC Unit, 28-TOPS/W and 1.5-TOPS/mm2 in 40nm. 1-2 - Kangping Hu, Joseph Incandela
A 13.1mm2 512 × 256 Multimodal CMOS Array for Spatiochemical Imaging of Bacterial Biofilms. 1-2 - Xueyong Zhang
A 915-1220 TOPS/W Hybrid In-Memory Computing based Image Restoration and Region Proposal Integrated Circuit for Neuromorphic Vision Sensors in 65nm CMOS. 1-2 - Avishek Biswas, Hetul Sanghvi, Mahesh Mehendale, G. Preet:
An area-efficient 6T-SRAM based Compute-In-Memory architecture with reconfigurable SAR ADCs for energy-efficient deep neural networks in edge ML applications. 1-2 - Ziyi Chang
A Battery-Less Crystal-Less 49.8µW Neural-Recording Chip Featuring Two-Tone RF Power Harvesting. 1-2 - Kuo-Ken Huang, Jonathan K. Brown, Richard K. Sawyer, Christopher J. Lukas
ULP Receivers in Self-Powered Industrial loT Applications: Challenges and Prospects. 1-8 - Hao Zhang
A 77μW 115dB-Dynamic-Range 586fA-Sensitivity Current-Domain Continuous-Time Zoom ADC with Pulse-Width-Modulated Resistor DAC and Background Offset Compensation Scheme. 1-2 - Jiahao Liu, Jianbiao Xiao
An Energy-Efficient Cardiac Arrhythmia Classification Processor using Heartbeat Difference based Classification and Event-Driven Neural Network Computation with Adaptive Wake-Up. 1-2 - Francesco Buccoleri, Simone Mattia Dartizio, Francesco Tesolin, Luca Avallone, Alessio Santiccioli, Agata Iesurum
A 9GHz 72fs-Total-lntegrated-Jitter Fractional-N Digital PLL with Calibrated Frequency Quadrupler. 1-2 - Mohammadreza Beikmirza, Yiyu Shen, Leo C. N. de Vreede, Morteza S. Alavi
A 1-to-4GHz Multi-Mode Digital Transmitter in 40nm CMOS Supporting 200MHz 1024-QAM OFDM signals with more than 23dBm/66% Peak Power/Drain Efficiency. 1-2 - Lei Zhao, Junyao Tang, Cheng Huang:
A Fully In-Package 4-Phase Fixed-Frequency DAB Hysteretic Controlled DC-DC Converter with Enhanced Efficiency, Load Regulation and Transient Response. 1-2 - Marcel Runge, Julius Edler, Dario Schmock, Tobias Kaiser, Friedel Gerfers:
A 30-MHz BW 74.6-dB SNDR 92-dB SFDR CT ΔΣ Modulator with Active Body-Bias DAC Calibration in 22nm FDSOI CMOS. 1-2 - Munehiko Nagatani, Hitoshi Wakita, Teruo Jyo, Tsutomu Takeya, Hiroshi Yamazaki, Yoshihiro Ogiso, Miwa Mutoh, Yuta Shiratori, Minoru Ida, Fukutaro Hamaoka, Masanori Nakamura, Takayuki Kobayashi, Hiroyuki Takahashi, Yutaka Miyamoto:
110-GHz-Bandwidth InP-HBT AMUX/ADEMUX Circuits for Beyond-1-Tb/s/ch Digital Coherent Optical Transceivers. 1-8 - Jessica D. Boles, Joshua J. Piel, Ng Elaine, Joseph E. Bonavia
Piezoelectric-Based Power Conversion: Recent Progress, Opportunities, and Challenges. 1-8 - Michella Rustom
Wireless Frequency-Division Multiplexed 3D Magnetic Localization for Low Power Sub-mm Precision Capsule Endoscopy. 1-2 - Jieyu Li
TICA: A 0.3V, Variation-Resilient 64-Stage Deeply-Pipelined Bitcoin Mining Core with Timing Slack Inference and Clock Frequency Adaption. 1-2 - Ayman Shabra, Yun-Shiang Shu, Shon-Hang Wen, Kuan-Dar Chen:
Design Techniques for High Linearity and Dynamic Range Digital to Analog Converters. 1-8 - Tuur Van Daele, Filip Tavernier:
A 400-to-12 V Fully Integrated Switched-Capacitor DC-DC Converter Achieving 119 mW/mm2 at 63.6 % Efficiency. 1-2 - Uisub Shin, Cong Ding
A 16-Channel 60µW Neural Synchrony Processor for Multi-Mode Phase-Locked Neurostimulation. 1-2 - Jaehoon Heo, Junsoo Kim, Wontak Han, Sukbin Lim
T-PIM: A 2.21-to-161.08TOPS/W Processing-In-Memory Accelerator for End-to-End On-Device Training. 1-2 - Shiyu Su, Mike Shuo-Wei Chen:
High-Speed Digital-to-Analog Converter Design Towards High Dynamic Range. 1-8 - Huseyin Ekin Sumbul
System-Level Design and Integration of a Prototype AR/VR Hardware Featuring a Custom Low-Power DNN Accelerator Chip in 7nm Technology for Codec Avatars. 1-8 - Loan Pham-Nguyen
An 86.7%-Efficient Three-Level Boost Converter with Active Voltage Balancing for Thermoelectric Energy Harvesting. 1-2 - Bowen Wang
A 0.14nJ/b 200Mb/s Quasi-Balanced FSK Transceiver with Closed-Loop Modulation and Sideband Energy Detection. 1-2 - Yangtao Dong, Chirn Chye Boon, Kaituo Yang, Zhe Liu:
A 2-GHz Dual-Path Sub-Sampling PLL with Ring VCO Phase Noise Suppression. 1-2 - Joohwan Kim, Junyoung Park, Jindo Byun, Changkyu Seol, Chang Soo Yoon, EunSeok Shin, Hyunyoon Cho, Youngdo Um, Sucheol Lee, Hyungmin Jin, Kwangseob Shin, Hyunsub Norbert Rie, Minsu Jung, Jin-Hee Park, Go-Eun Cha, Minjae Lee, YoungMin Kim, Byeori Han, Yuseong Jeon, Jisun Lee, Hyejeong So, Sungduk Kim, Wansoo Park, Tae Young Kim, Youngdon Choi, Jung-Hwan Choi, Hyungjong Ko, Sang-Hyun Lee:
A 60-Gb/s/pin single-ended PAM-4 transmitter with timing skew training and low power data encoding in mimicked 10nm class DRAM process. 1-2 - Mohamed R. Abdelhamid, Unsoo Ha, Utsav Banerjee, Fadel Adib, Anantha P. Chandrakasan:
Wireless, Batteryless, and Secure Implantable System-on-a-Chip for 1.37mmHg Strain Sensing with Bandwidth Reconfigurability for Cross-Tissue Adaptation. 1-2 - Hariprasad Chandrakumar, Thomas William Brown, Dimitri Frolov, Zinia Tuli, Iwen Huang, Said Rami:
A 48dB-SFDR, 43dB-SNDR, 50GS/s 9-bit 2x-interleaved Nyquist DAC in Intel 16. 1-2 - Naresh R. Shanbhag, Saion K. Roy:
Comprehending In-memory Computing Trends via Proper Benchmarking. 1-7 - Zhixian Deng, Huizhen Jenny Qian, Changxuan Han, Yifan Li, Xun Luo:
A 3.8-dB NF, 23-40GHz Phased-Array Receiver with 14-Bit Phase & Gain Manager and Calibration-Free Dual-Mode 28-52dB Image Rejection Ratio for 5G NR. 1-2 - Yongxin Li
A 20µs turn-on time, 24kHz resolution, 1.5-100MHz digitally programmable temperature-compensated clock generator with 7.5ppm/°C inaccuracy. 1-2 - Shenggao Li
Interconnect in the Era of 3DIC. 1-5 - Edward Jongyoon Choi, Injun Choi, Chanhee Jeon, Gichan Yun
A 133.6TOPS/W Compute-In-Memory SRAM Macro with Fully Parallel One-Step Multi-Bit Computation. 1-2 - Nimesh Nadishka Miral, Karan Sohal, Danilo Manstretta, Rinaldo Castello:
Filtering Trans-Impedance Amplifiers: from mW of Power to GHz of Bandwidth. 1-8 - Shenglong Zhuo, Lei Zhao, Tao Xia, Lei Wang, Shi Shi, Yifan Wu, Chang Liu, Chill Wang, Yuwei Wang, Yuan Li, Hengwei Yu
Solid-State dToF LiDAR System Using an Eight-Channel Addressable, 20W/Ch Transmitter, and a 128x128 SPAD Receiver with SNR-Based Pixel Binning and Resolution Upscaling. 1-2 - Zixiao Lin, Yan Lu, Fangyu Mao, Chuang Wang
All Rivers Flow to the Sea: A High Power Density Wireless Power Receiver with Split-Dual-Path Rectification and Hybrid-Quad-Path Step-Down Conversion. 1-2 - Ruichang Ma, Haikun Jia, Wei Deng, Zhihua Wang, Baoyong Chi:
A 12.5-to-15.4GHz, -118.9dBc/Hz PN at 1MHz offset, and 191.0dBc/Hz FoM VCO with Common-Mode Resonance Expansion and Simultaneous Differential 2ND-Harmonic Output using a Single Three-Coil Transformer in 65nm CMOS. 1-2 - Zhiyu Chen, Qing Jin
DCT-RAM: A Driver-Free Process-In-Memory 8T SRAM Macro with Multi-Bit Charge-Domain Computation and Time-Domain Quantization. 1-2 - Dhruv Patel, Alireza Sharif Bakhtiar, Anthony Chan Carusone:
A 112 Gb/s -8.2 dBm Sensitivity 4-PAM Linear TIA in 16nm CMOS with Co-Packaged Photodiodes. 1-2 - Sandeep Reddy Kukunuru
A 93.7%-Efficiency 5-Ratio Switched-Photovoltaic DC-DC Converter. 1-2 - Boce Lin, Tzu-Yuan Huang, Amr Ahmed
A 23-37GHz Autonomous Two-Dimensional MIMO Receiver Array with Rapid Full-FoV Spatial Filtering for Unknown Interference Suppression. 1-2 - Hongyu Wang
A 39pJ/label 1920x1080 165.7 FPS Block PatchMatch Based Stereo Matching Processor on FPGA. 1-2 - Supreet Jeloka, Brian Cline, Shidhartha Das, Benoit Labbe, Alejandro Rico, Rainer Herberholz, Javier A. DeLaCruz, Rahul Mathur, Shawn Hung:
System technology co-optimization and design challenges for 3D IC. 1-6 - Atefeh Sohrabizadeh, Yuze Chi, Jason Cong:
StreamGCN: Accelerating Graph Convolutional Networks with Streaming Processing. 1-8 - Kyeongho Eom, Han-Sol Lee, Minju Park, Hyung-Min Lee
A 92%-Efficiency Inductor-Charging Switched-Capacitor Stimulation System with Level-Adaptive Duty Modulation and Offset Charge Balancing for Muscular Stimulation. 1-2 - Christoph Rindfleisch, Jens Otten, Bernhard Wicht
A Highly-Integrated 20-300V 0.5W Active-Clamp Flyback DCDC Converter with 76.7% Peak Efficiency. 1-2 - Seungsik Moon
A 2.86Gb/s Fully-Flexible MU-MIMO Processor for Jointly Optimizing User Selection, Power Allocation, and Precoding in 28nm CMOS Technology. 1-2 - Justin Yonghui Kim
A 2GHz voltage mode power scalable RF-Front-End with 2.5dB-NF and 0.5dBm-1dBCP. 1-2 - Maitreyi Ashok, Edlyn V. Levine, Anantha P. Chandrakasan:
Randomized Switching SAR (RS-SAR) ADC Protections for Power and Electromagnetic Side Channel Security. 1-2 - Yijie Wei, Xi Chen, Jie Gu:
A 65nm Implantable Gesture Classification SoC for Rehabilitation with Enhanced Data Compression and Encoding for Robust Neural Network Operation Under Wireless Power Condition. 1-2 - Aviral Pandey, Sina Faraji Alamouti, Justin Doong, Ryan Kaveh, Cem Yalcin, Mohammad Meraj Ghanbari, Rikky Muller:
A 6.8µW AFE for Ear EEG Recording with Simultaneous Impedance Measurement for Motion Artifact Cancellation. 1-2 - R. Mathur, M. Kumar, Vivek Asthana, S. Aggarwal, S. Gupta, D. Wanjul, A. Baradia, S. Thota, P. Jain, B. Zheng, A. Cubeta, S. Thyagarajan, A. Chen, Y. K. Chong:
5GHz SRAM for High-Performance Compute Platform in 5nm CMOS. 1-2 - Stefano Pellerano, Sushil Subramanian, Jong Seok Park, Bishnu Patra, Todor Mladenov, Xiao Xue
Cryogenic CMOS for Qubit Control and Readout. 1-8 - Salvatore Levantino:
Recent Advances in High-Performance Frequency Synthesizer Design. 1-7 - Mingqiang Guo
A 10b 700MS/s single-channel 1b/cycle SAR ADC using a monotonic-specific feedback SAR logic with power-delay-optimized unbalanced N/P-MOS sizing. 1-2 - Mark J. W. Rodwell, Ahmed S. H. Ahmed, Munkyo Seo, Utku Soylu, Amirreza Alizadeh, Navid Hosseinzadeh:
IC and Array Technologies for 100-300GHz Wireless. 1-5 - Hossein Hashemi
A Review of Silicon Photonics LiDAR. 1-8 - Sameer Sonkusale:
Smart Threads for Tissue-Embedded Bioelectronics. 1-7 - Chen Tan, Wei Huang, Yonghui Fan, Jing Li, Chuanhao Yu, Wenbo Shi, Shiti Huang, Zhenyu Yin, Chenfan Cao, Lei Jing, Zhixiong Ren, Xiaoyan Gui, Bing Zhang, Dan Li, Li Geng:
A 10/2.5-Gb/s Hyper-Supplied CMOS Low-Noise Burst-Mode TIA with Loud Burst Protection and Gearbox Automatic Offset Cancellation for XGS-PON. 1-2 - Chuxiong Lin, Weifeng He, Yannan Sun, Lin Shao, Bo Zhang, Jun Yang, Mingoo Seok:
MPAM: Reliable, Low-Latency, Near-Threshold-Voltage Multi-Voltage/Frequency-Domain Network-on-Chip with Metastability Risk Prediction and Mitigation. 1-2 - Muya Chang, Xunzhao Yin, Zoltán Toroczkai, Xiaobo Hu, Arijit Raychowdhury:
An Analog Clock-free Compute Fabric base on Continuous-Time Dynamical System for Solving Combinatorial Optimization Problems. 1-2 - Qiuyang Lin, Christina Avidikou, Filip Tavernier, Nick Van Helleputte:
Photoplethysmography (PPG) Sensor Circuit Design Techniques. 1-8 - Yan He, Qixuan Yu, Kaiyuan Yang
A Lossless and Modeling Attack-Resistant Strong PUF with <4E-8 Bit Error Rate. 1-2 - Archisman Ghosh, Dong-Hyun Seo, Debayan Das, Santosh Ghosh, Shreyas Sen:
A Digital Cascoded Signature Attenuation Countermeasure with Intelligent Malicious Voltage Drop Attack Detector for EM/Power SCA Resilient Parallel AES-256. 1-2 - Muhammad Ali Montazerolghaem, Leo C. N. de Vreede, Masoud Babaie:
A 0.5-3GHz Receiver with a Parallel Preselect Filter Achieving 120dB/dec Channel Selectivity and +28dBm Out-of-Band IIP3. 11-12 - Hongchang Qiao, Chenchang Zhan:
A 19-30ppm/°C Temperature Coefficient Sub-Nanowatt CMOS Voltage Reference with 10-µA Sourcing Capability. 1-2 - Jyothi Bhaskarr Velamala, Siang-jhih Sean Wu, Padma Penmatsa, Kuan-Yueh James Shen, David Johnston, Rachael J. Parker:
PVT Tolerant Zero Bit-Error-Rate Physical Unclonable Function Exploiting Hot Carrier Injection Aging in 7nm FinFET Technology. 1-2 - Bowen Wang
A 7.25-7.75GHz 5.9mW UWB Transceiver with -23.8dBm NBI Tolerance and 1.5cm Ranging Accuracy Using Uncertain IF and Pulse-Triggered Envelope/Energy Detection. 1-2 - David J. Allstot, Un-Ku Moon, Gabor C. Temes:
Switched-Capacitor Circuits. 1-8 - Archisman Ghosh, Jose Maria Bermudo Mera, Angshuman Karmakar
A 334uW 0.158mm2 Saber Learning with Rounding based Post-Quantum Crypto Accelerator. 1-2 - Tianxiang Qu
A 1.8GΩ-Input-Impedance 0.15µV-Input-Referred-Ripple Chopper Amplifier with Local Positive Feedback and SAR-Assisted Ripple Reduction. 1-2 - Donghee Cho, Hyungjoo Cho, Sein Oh, Yoontae Jung, Sohmyung Ha
A Single-Mode Dual-Path Buck-Boost Converter with Reduced Inductor Current Across All Duty Cases Achieving 95.58% Efficiency at 1A in Boost Operation. 1-2 - Tianshi Xie, Jianglin Zhu, Tom Byrd, Dragan Maksimovic, Hanh-Phuc Le
A 0.66 W/mm2 Power Density, 92.4% Peak Efficiency Hybrid Converter with nH-Scale Inductors for 12 V System. 1-2 - Rajit Manohar:
Hardware/software Co-design for Neuromorphic Systems. 1-5 - Jeongseok Lee, Doohwan Jung, David Joseph Munzer, Hua Wang:
A Compact Wideband Joint Bidirectional Class-G Digital Doherty Switched-Capacitor Transmitter and N-Path Quadrature Receiver through Capacitor Bank Sharing. 1-2 - Wei Shi, Xing Wang, Xiyuan Tang, Abhishek Mukherjee, Raviteja Theertham, Shanthi Pavan, Lu Jie, Nan Sun:
A 0.37mm2 250kHz-BW 95dB-SNDR CTDSM with Low-Cost 2nd-order Vector-Quantizer DEM. 1-2 - Yuncheng Lu, Zehao Li, Yuzong Chen
A 181µW Real-Time 3-D Hand Gesture Recognition System based on Bi-directional Convolution and Computing-Efficient Feature Clustering. 1-2 - Woojoong Jung, Minsu Kim, Hyunjun Park, Sungmin Yoo, Tae-Hwang Kong, Jun-Hyeok Yang, Michael Choi, Jongshin Shin, Hyung-Min Lee
A Hybrid Always-Dual-Path Recursive Step-Down Converter Using Adaptive Switching Level Control Achieving 95.4% Efficiency with 288mΩ Large-DCR Inductor. 1-2 - Yuanming Zhu
A Jitter-Robust 40Gb/s ADC-Based Multicarrier Receiver Front End in 22nm FinFET. 1-2 - Xin Ming, Zhiyi Lin, Tian-yi Sun, Yao Qin, Yuan-Yuan Liu, Chun-wang Zhuang, Zhao-ji Li, Bo Zhang:
An Up to 10MHz 6.8% Minimum Duty Ratio GaN Driver with Dual-MOS-Switches Bootstrap and Adaptive Short-Pulse Based High-CMTI Level Shifter Achieving 6.05% Efficiency Improvement. 1-2 - Qiang Liu, Zishen Wan, Bo Yu, Weizhuang Liu, Shaoshan Liu, Arijit Raychowdhury:
An Energy-Efficient and Runtime-Reconfigurable FPGA-Based Accelerator for Robotic Localization Systems. 1-2 - Renze Gan, Liangjian Lyu, Geng Mu, Chuanjin Richard Shi:
A Neural Recording Analog Front-End with Exponentially Tunable Pseudo Resistors and On-Chip Digital Frequency Calibration Loop Achieving 3.4% Deviation of High-Pass Cutoff Frequency in 5-to-500 Hz Range. 1-2 - Zekun Li
A 220 GHz Sliding-IF Quadrature Transmitter With 38-dB Conversion Gain and 8-dBm Psat in 0.13-µm SiGe BiCMOS. 1-2 - Xiaofeng Guo, Run Chen, Rongfeng Xu, Bin Li, Zhenqi Chen:
A Calibration-Free 13b 625MS/s Tri-State Pipelined-SAR ADC with PVT-Insensitive Inverter-Based Residue Amplifier. 1-2
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