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Mahesh Mehendale
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2020 – today
- 2024
- [j4]Adithya Krishna
, Srikanth Rohit Nudurupati
RAMAN: A Reconfigurable and Sparse tinyML Accelerator for Inference on Edge. IEEE Internet Things J. 11(14): 24831-24845 (2024) - [c54]Adithya Krishna, Ashwin Rajesh, Hitesh Pavan Oleti, Anand Chauhan, Shankaranarayanan H, André van Schaik, Mahesh Mehendale, Chetan Singh Thakur:
Live Demonstration: Real-time audio and visual inference on the RAMAN TinyML accelerator. ISCAS 2024: 1 - 2023
- [c53]Adithya Krishna, Hitesh Pavan Oleti, Anand Chauhan, H. Shankaranarayanan, André van Schaik, Mahesh Mehendale, Chetan Singh Thakur:
Live Demonstration: Audio Inference using Neuromorphic Cochlea on RAMAN Accelerator. BioCAS 2023: 1 - [c52]Adithya Krishna, Vignesh Ramanathan, Satyapreet Singh Yadav
A Sparsity-driven tinyML Accelerator for Decoding Hand Kinematics in Brain-Computer Interfaces. BioCAS 2023: 1-5 - [i2]Adithya Krishna, Srikanth Rohit Nudurupati, Chandana D. G, Pritesh Dwivedi, André van Schaik, Mahesh Mehendale, Chetan Singh Thakur:
RAMAN: A Re-configurable and Sparse tinyML Accelerator for Inference on Edge. CoRR abs/2306.06493 (2023) - 2022
- [c51]Avishek Biswas, Hetul Sanghvi, Mahesh Mehendale, G. Preet:
An area-efficient 6T-SRAM based Compute-In-Memory architecture with reconfigurable SAR ADCs for energy-efficient deep neural networks in edge ML applications. CICC 2022: 1-2 - 2021
- [c50]Vipul Singhal, Rajat Chauhan, Vinod Menezes, R. R. Manikandan, Raveesh Magod
150nA IQ, Quad Input - Quad Output, Intelligent Integrated Power Management for IoT Applications. VLSID 2021: 169-174 - 2020
- [c49]Hassan Dbouk, Hetul Sanghvi, Mahesh Mehendale, Naresh R. Shanbhag:
DBQ: A Differentiable Branch Quantizer for Lightweight Deep Neural Networks. ECCV (27) 2020: 90-106 - [i1]Hassan Dbouk, Hetul Sanghvi, Mahesh Mehendale, Naresh R. Shanbhag:
DBQ: A Differentiable Branch Quantizer for Lightweight Deep Neural Networks. CoRR abs/2007.09818 (2020)
2010 – 2019
- 2018
- [c48]R. R. Manikandan, Vipul Kumar Singhal, Rajat Chauhan, Vinod Menezes, Mahesh Mehendale:
A 1.2 pJ/cycle KHz Timer Circuit for Heavily Duty-Cycled Systems. VLSID 2018: 171-176 - 2017
- [c47]Takashi Hashimoto, Mahesh Mehendale, Byeong-Gyu Nam:
Session 14 overview: Deep-learning processors. ISSCC 2017: 236-237 - 2016
- [c46]Mahesh Mehendale, Luke Shin:
Session 4 overview: Digital processors. ISSCC 2016: 70-71 - [c45]Vivek De, Kerry Bernstein, Takefumi Yoshikawa, Yusuf Leblebici, Marian Verhelst, Mahesh Mehendale, Makoto Nagata:
F1: Designing secure systems: Manufacturing, circuits and architectures. ISSCC 2016: 492-494 - [c44]Nagendra Gulur, R. Govindarajan, Mahesh Mehendale:
MicroRefresh: Minimizing Refresh Overhead in DRAM Caches. MEMSYS 2016: 350-361 - 2015
- [c43]Dipan Kumar Mandal, Mihir Mody, Mahesh Mehendale, Naresh Yadav, Ghone Chaitanya, Piyali Goswami, Hetul Sanghvi, Niraj Nandan:
Accelerating H.264/HEVC video slice processing using application specific instruction set processor. ICCE 2015: 408-411 - [c42]Vipul Kumar Singhal, Vinod Menezes, Srinivasa Chakravarthy, Mahesh Mehendale:
8.3 A 10.5μA/MHz at 16MHz single-cycle non-volatile memory access microcontroller with full state retention at 108nA in a 90nm process. ISSCC 2015: 1-3 - [c41]Nagendra Dwarakanath Gulur, Mahesh Mehendale, Ramaswamy Govindarajan:
A Comprehensive Analytical Performance Model of DRAM Caches. ICPE 2015: 157-168 - 2014
- [c40]Hetul Sanghvi, Mihir N. Mody, Niraj Nandan, Mahesh Mehendale, Subrangshu Das, Dipan Kumar Mandal, Nainala Vyagrheswarudu, Vijayavardhan Baireddy, Pavan Shastry:
A monolithic programmable Ultra-HD video codec engine. ICASSP 2014: 1399-1403 - [c39]Hetul Sanghvi, Mihir N. Mody, Niraj Nandan, Mahesh Mehendale, Subrangshu Das, Dipan Kumar Mandal, Pavan Shastry:
A 28nm programmable and low power ultra-HD video codec engine. ISCAS 2014: 558-561 - [c38]Nagendra Dwarakanath Gulur, Mahesh Mehendale, R. Manikantan, R. Govindarajan:
Bi-Modal DRAM Cache: Improving Hit Rate, Hit Latency and Bandwidth. MICRO 2014: 38-50 - [c37]Nagendra Gulur, Mahesh Mehendale, Raman Manikantan, Ramaswamy Govindarajan:
ANATOMY: an analytical model of memory system performance. SIGMETRICS 2014: 505-517 - 2012
- [c36]Nagendra Dwarakanath Gulur, R. Manikantan, Mahesh Mehendale, R. Govindarajan:
Multiple sub-row buffers in DRAM: unlocking performance and energy improvement opportunities. ICS 2012: 257-266 - [c35]Mahesh Mehendale, Subrangshu Das, Mohit Sharma, Mihir N. Mody, Ratna Reddy, Joseph P. Meehan
A true multistandard, programmable, low-power, full HD video-codec engine for smartphone SoC. ISSCC 2012: 226-228 - 2011
- [j3]Ajit Gupte, Bharadwaj Amrutur, Mahesh Mehendale, Ajit V. Rao, Madhukar Budagavi:
Memory Bandwidth and Power Reduction Using Lossy Reference Frame Compression in Video Encoding. IEEE Trans. Circuits Syst. Video Technol. 21(2): 225-230 (2011) - [c34]Nagendra Dwarakanath Gulur, R. Manikantan, R. Govindarajan, Mahesh Mehendale:
Row-Buffer Reorganization: Simultaneously Improving Performance and Reducing Energy in DRAMs. PACT 2011: 189-190
2000 – 2009
- 2006
- [j2]Subash Chandar G., Mahesh Mehendale, R. Govindarajan:
Area and Power Reduction of Embedded DSP Systems using Instruction Compression and Re-configurable Encoding. J. VLSI Signal Process. 44(3): 245-267 (2006) - [c33]Mahesh Mehendale:
SoC - The Road Ahead. VLSI Design 2006: 40 - 2004
- [c32]Mahesh Mehendale:
Challenges in the Design of Embedded Real-time DSP SoCs. VLSI Design 2004: 507-511 - 2003
- [c31]Chi-Foon Chan, Deirdre Hanford, Jian Yue Pan, Narendra V. Shenoy, Mahesh Mehendale, A. Vasudevan, Shaojun Wei:
Emerging markets: design goes global. DAC 2003: 195 - [c30]Amitabh Menon, S. K. Nandy, Mahesh Mehendale:
Multivoltage scheduling with voltage-partitioned variable storage. ISLPED 2003: 298-301 - 2001
- [c29]Subash Chandar G., Mahesh Mehendale, R. Govindarajan:
Area and Power Reduction of Embedded DSP Systems using Instruction Compression and Re-Configurable Encoding. ICCAD 2001: 631-634 - [c28]Mahesh Mehendale, Santhosh Kumar Amanna:
Functional Verification of Programmable DSP Cores. VLSI Design 2001: 16-17 - [c27]Ajit Gupte, Mahesh Mehendale, Ramesh Ramamritham, Deepa Nair:
Performance Considerations in Embedded DSP based System-On-a-Chip Designs. VLSI Design 2001: 36-41 - [c26]Vikas Agrawal, Anand Pande, Mahesh Mehendale:
High Level Synthesis Of Multi-Precision Data Flow Graphs. VLSI Design 2001: 411-416 - 2000
- [c25]Mahesh Mehendale, Sunil D. Sherlekar:
Power Reduction Techniques for Portable DSP Applications. VLSI Design 2000: 3 - [c24]M. N. Mahesh, Mahesh Mehendale:
Low Power Realization of Residue Number System Based FIR Filters. VLSI Design 2000: 30-33
1990 – 1999
- 1999
- [c23]Sunsil Sinha, Mahesh Mehendale:
Integrated IC design approach based on software engineering paradigm. CICC 1999: 53-56 - [c22]M. N. Mahesh, Mahesh Mehendale:
Improving performance of high precision signal processing algorithms on programmable DSPs. ISCAS (3) 1999: 488-491 - [c21]Mahesh Mehendale, Sunil D. Sherlekar:
Low Power Code Generation of Multiplication-free Linear Transforms. VLSI Design 1999: 42-47 - [c20]M. N. Mahesh, Satrajit Gupta, Mahesh Mehendale:
Improving Area Efficiency of Residue Number System based Implementation of DSP Algorithms. VLSI Design 1999: 340-345 - 1998
- [j1]Mahesh Mehendale, Sunil D. Sherlekar, G. Venkatesh:
Low-power realization of FIR filters on programmable DSPs. IEEE Trans. Very Large Scale Integr. Syst. 6(4): 546-553 (1998) - [c19]Mahesh Mehendale, Amit Sinha, Sunil D. Sherlekar:
Low Power Realization of FIR Filters Implemented using Distributed Arithmetic. ASP-DAC 1998: 151-156 - [c18]Mahesh Mehendale, Sunil D. Sherlekar, G. Venkatesh:
Algorithmic and Architectural Transformations for Low Power Realization of FIR Filters. VLSI Design 1998: 12-17 - [c17]Mahesh Mehendale, Sunil D. Sherlekar, G. Venkatesh:
Extensions to Programmable DSP architectures for Reduced Power Dissipation. VLSI Design 1998: 37- - [c16]Amit Sinha, Mahesh Mehendale:
mproving Area Efficiency of FIR Filters Implemented Using Distributed Arithmetic. VLSI Design 1998: 104-109 - [c15]Mahesh Mehendale, Somdipta Basu Roy, Sunil D. Sherlekar, G. Venkatesh:
Coefficient Transformations for Area-Efficient Implementation of Multiplier-less FIR Filters. VLSI Design 1998: 110-115 - 1997
- [c14]Mahesh Mehendale, Sunil D. Sherlekar, G. Venkatesh:
Area-Delay Tradeoff in Distributed Arithmetic Based Implementation of FIR Filters. VLSI Design 1997: 124-129 - 1996
- [c13]Mahesh Mehendale, G. Venkatesh, Sunil D. Sherlekar:
Optimized Code Generation of Multiplication-free Linear Transforms. DAC 1996: 41-46 - [c12]Mahesh Mehendale, Sunil D. Sherlekar, G. Venkatesh:
Low power realization of FIR filters using multirate architectures. VLSI Design 1996: 370-375 - 1995
- [c11]Mahesh Mehendale, Sunil D. Sherlekar, G. Venkatesh:
Techniques for low power realization for FIR filters. ASP-DAC 1995 - [c10]Mahesh Mehendale, Sunil D. Sherlekar, G. Venkatesh:
Synthesis of multiplier-less FIR filters with minimum number of additions. ICCAD 1995: 668-671 - [c9]Mahesh Mehendale, M. K. Ram Prasad:
AATMA: an algorithm for technology mapping for antifuse-based FPGAs. VLSI Design 1995: 69-74 - 1994
- [c8]Mahesh Mehendale:
Impact of Logic Module Routing Flexibility on the Routability of Antifuse-Based Channelled FPGA Architectures. VLSI Design 1994: 233-236 - [c7]Mahesh Mehendale, Biswadip Mitra:
An Integrated Approach to State Assignment and Sequential Element Selection for FSM Synthesis. VLSI Design 1994: 369-372 - 1993
- [c6]Mahesh Mehendale:
MIM: Logic Module Independent Technology Mapping for Design and Evaluation of Antifuse-based FPGAs. DAC 1993: 219-223 - [c5]Mahesh Mehendale, Kaushik Roy:
Estimating Area Efficiency of Antifuse Based Channelled FPGA Architectures. VLSI Design 1993: 100-103 - 1992
- [c4]Mahesh Mehendale:
A System for Behavior Extraction from FPGA Implementations of Synchronous Designs. VLSI Design 1992: 320-321 - 1991
- [c3]Mahesh Mehendale:
An approach to design flow management in CAD frameworks. EURO-DAC 1991: 38-42 - [c2]Mahesh Mehendale, P. Murugavel, M. Poornima:
SLIM: A System for ASIC Library Management. ICCAD 1991: 144-147
1980 – 1989
- 1989
- [c1]Sattam Dasgupta, Mahesh Mehendale, V. R. Sudershan, Rajeev Jain, Nagaraj Subramanyam, James Hochschild:
FDT-a design tool for switched capacitor filters. ICCAD 1989: 446-449
Coauthor Index
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