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Bernhard Wicht
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2020 – today
- 2024
- [j13]Arindam Mishra
, Wei Zhu
A Dual-Inductor Ladder Buck Converter for Li-Ion Battery-Operated Sub-Volt SoCs. IEEE J. Solid State Circuits 59(2): 563-573 (2024) - [c37]Jesko Flemming
A DAC Sharing and Linearization Technique for Time-Interleaved Incremental Delta-Sigma ADCs. ISCAS 2024: 1-5 - [c36]Niklas Deneke, Bernhard Wicht:
31.10 A Fully integrated 500V, 6.25MHz GaN-IC for Totem-Pole PFC Off-Line Power Conversion. ISSCC 2024: 514-516 - [c35]Jesko Flemming, Timon Rogge, Bernhard Wicht, Pascal Witte:
A Hardware Efficient Digital DAC Linearization Topology for Delta-Sigma ADCs. SMACD 2024: 1-4 - 2023
- [c34]Adrian Gehl, Kyrylo Cherniak, Olga Kharko, Gianluca Marin, Petru Bacinski, Frank Prämaßing, Bernhard Wicht:
A 2-8V Vin 670mA Scalable Multi-Ratio SC DCDC Converter for MCU Integration in 28nm CMOS Achieving 91% Peak Efficiency. ESSCIRC 2023: 425-428 - [c33]Jesko Flemming
A Noise-Canceling SMASH Architecture for Discrete-Time Bandpass Delta-Sigma ADCs. ISCAS 2023: 1-5 - [c32]Jesko Flemming
Stability Analysis for Frequency Tunable Bandpass Delta-Sigma ADC Architectures. SMACD 2023: 1-4 - 2022
- [j12]Christoph Rindfleisch
A 110/230 V AC and 15-400 V DC 0.3 W Power-Supply IC With Integrated Active Zero-Crossing Buffer. IEEE J. Solid State Circuits 57(12): 3816-3824 (2022) - [c31]Christoph Rindfleisch, Jens Otten, Bernhard Wicht:
A Highly-Integrated 20-300V 0.5W Active-Clamp Flyback DCDC Converter with 76.7% Peak Efficiency. CICC 2022: 1-2 - [c30]Christoph Rindfleisch, Bernhard Wicht:
A 110V/230V 0.3W Offline Chip-Scale Power Supply with Integrated Active Zero-Crossing Buffer and Voltage-Interval-Based Dual-Mode Control. ISSCC 2022: 1-3 - 2021
- [j11]Christoph Rindfleisch
A Resonant One-Step 325 V to 3.3-10 V DC-DC Converter With Integrated Power Stage Benefiting From High-Voltage Loss-Reduction Techniques. IEEE J. Solid State Circuits 56(11): 3511-3520 (2021) - [c29]Min Chen, Bernhard Wicht
Session 33 Overview: High-Voltage, GaN and Wireless Power Power Management Subcommittee. ISSCC 2021: 458-459 - 2020
- [j10]Maik Kaufmann
A Monolithic GaN-IC With Integrated Control Loop for 400-V Offline Buck Operation Achieving 95.6% Peak Efficiency. IEEE J. Solid State Circuits 55(12): 3169-3178 (2020) - [c28]Maik Kaufmann
Long, Short, Monolithic - The Gate Loop Challenge for GaN Drivers: Invited Paper. CICC 2020: 1-5 - [c27]Christoph Rindfleisch
11.3 A One-Step 325V to 3.3-to-10V 0.5W Resonant DC-DC Converter with Fully Integrated Power Stage and 80.7% Efficiency. ISSCC 2020: 194-196 - [c26]Maik Kaufmann
18.2 A Monolithic E-Mode GaN 15W 400V Offline Self-Supplied Hysteretic Buck Converter with 95.6% Efficiency. ISSCC 2020: 288-290
2010 – 2019
- 2019
- [j9]Youngcheol Chae
Introduction to the Special Issue on the 2019 IEEE International Solid-State Circuits Conference (ISSCC). IEEE J. Solid State Circuits 54(12): 3243-3246 (2019) - [c25]Peter Renz
A Fully Integrated 85%-Peak-Efficiency Hybrid Multi Ratio Resonant DC-DC Converter with 3.0-to-4.5V Input and 500μA -to-120mA Load Range. ISSCC 2019: 156-158 - [c24]Sebastian Kiesel, Thomas Kern, Bernhard Wicht, Helmut Graeb:
A 30 ns 16 Mb 2 b/cell Embedded Flash with Ramped Gate Time-Domain Sensing Scheme for Automotive Application. VLSI-DAT 2019: 1-4 - 2018
- [j8]Francesco Santoro
A Hysteretic Buck Converter With 92.1% Maximum Efficiency Designed for Ultra-Low Power and Fast Wake-Up SoC Applications. IEEE J. Solid State Circuits 53(6): 1856-1868 (2018) - [j7]Juergen Wittmann
A 48-V Wide-Vin 9-25-MHz Resonant DC-DC Converter. IEEE J. Solid State Circuits 53(7): 1936-1944 (2018) - [j6]Achim Seidel
Integrated Gate Drivers Based on High-Voltage Energy Storing for GaN Transistors. IEEE J. Solid State Circuits 53(12): 3446-3454 (2018) - [c23]Tobias Funk, Bernhard Wicht:
A fully integrated DC to 75 MHz current sensing circuit with on-chip Rogowski coil. CICC 2018: 1-4 - [c22]Daniel Lutz, Achim Seidel, Bernhard Wicht:
A 50V, 1.45ns, 4.1pJ High-Speed Low-Power Level Shifter for High-Voltage DCDC Converters. ESSCIRC 2018: 126-129 - [c21]Samuel Quenzer-Hohmuth, Steffen Ritzmann, Thoralf Rosahl, Bernhard Wicht:
A Boost Converter with 3-6V Input and Fast Transient Digital Control Comprising a 90 ns-Latency Live-Tracking Window ADC. ESSCIRC 2018: 130-133 - [c20]Achim Seidel, Bernhard Wicht
A fully integrated three-level 11.6nC gate driver supporting GaN gate injection transistors. ISSCC 2018: 384-386 - [c19]Axel Thomsen, Bernhard Wicht, Pieter Harpe, Man Kay Law, Young Cheol Chae:
F6: Advances in energy efficient analog design. ISSCC 2018: 517-519 - 2017
- [c18]Juergen Wittmann, Tobias Funk, Thoralf Rosahl, Bernhard Wicht:
A 12-48 V wide-vin 9-15 MHz soft-switching controlled resonant DCDC converter. ESSCIRC 2017: 348-351 - [c17]Achim Seidel, Bernhard Wicht
25.3 A 1.3A gate driver for GaN with fully integrated gate charge buffer capacitor delivering 11nC enabled by high-voltage energy storing. ISSCC 2017: 432-433 - [c16]Sebastian Kiesel, Thomas Kern, Bernhard Wicht
Time-domain ramped gate sensing for embedded multi-level flash in automotive applications. MWSCAS 2017: 691-694 - 2016
- [j5]Juergen Wittmann, Alexander Barner, Thoralf Rosahl, Bernhard Wicht
An 18 V Input 10 MHz Buck Converter With 125 ps Mixed-Signal Dead Time Control. IEEE J. Solid State Circuits 51(7): 1705-1715 (2016) - [c15]Alexis Schindler, Benno Koeppl, Ansgar Pottbaecker, Markus Zannoth, Bernhard Wicht
Gate driver with 10 / 15ns in-transition variable drive current and 60% reduced current dip. ESSCIRC 2016: 325-328 - [c14]Daniel Lutz
A 120/230 Vrms-to-3.3V micro power supply with a fully integrated 17V SC DCDC converter. ESSCIRC 2016: 449-452 - [c13]Daniel Lutz
12.4 A 10mW fully integrated 2-to-13V-input buck-boost SC converter with 81.5% peak efficiency. ISSCC 2016: 224-225 - [c12]Peter Renz
A 40V current sensing circuit with fast on/off transition for high-voltage power management. MWSCAS 2016: 1-4 - 2015
- [j4]Achim Seidel, Marco Salvatore Costa, Joachim Joos, Bernhard Wicht
Area Efficient Integrated Gate Drivers Based on High-Voltage Charge Storing. IEEE J. Solid State Circuits 50(7): 1550-1559 (2015) - [c11]Alexis Schindler, Benno Koeppl, Bernhard Wicht:
EMC and switching loss improvement for fast switching power stages by di/dt, dv/dt optimization with 10ns variable current source gate driver. EMC Compo 2015: 18-23 - [c10]Juergen Wittmann, Alexander Barner, Thoralf Rosahl, Bernhard Wicht
A 12V 10MHz buck converter with dead time control based on a 125 ps differential delay chain. ESSCIRC 2015: 184-187 - [c9]Tobias Funk, Juergen Wittmann, Thoralf Rosahl, Bernhard Wicht
A 20 V, 8 MHz resonant DCDC converter with predictive control for 1 ns resolution soft-switching. ISCAS 2015: 1742-1745 - 2014
- [c8]Juergen Wittmann, Thoralf Rosahl, Bernhard Wicht
A 50V high-speed level shifter with high dv/dt immunity for multi-MHz DCDC converters. ESSCIRC 2014: 151-154 - [c7]Achim Seidel, Marco Salvatore Costa, Joachim Joos, Bernhard Wicht
Bootstrap circuit with high-voltage charge storing for area efficient gate drivers in power management systems. ESSCIRC 2014: 159-162 - 2013
- [c6]Alexis Schindler, Benno Koeppl, Bernhard Wicht:
EMC analysis of current source gate drivers. EMC Compo 2013: 101-106 - [c5]Moris Lin, Yung-Sheng Huang, Andreas Ehrhart, Yu-Huei Lee, Chao-Chang Chiu, Bernhard Wicht
Authentic mode-toggled detector with fast transient response under wide load range buck-boost converter. ISCAS 2013: 2952-2955 - 2011
- [c4]Juergen Wittmann, Bernhard Wicht
EMC influence of the charge pump in linear regulators - Design, simulation and measurements. ISCAS 2011: 1359-1362
2000 – 2009
- 2009
- [c3]Stefan Herzer, Sumeet Kulkarni, Maciej Jankowski, Jochen Neidhardt, Bernhard Wicht:
Capacitive-coupled current sensing and Auto-ranging slope compensation for current mode SMPS with wide supply and frequency range. ESSCIRC 2009: 140-143 - 2008
- [j3]Michael Wendt, Lenz Thoma, Bernhard Wicht
A Configurable High-Side/Low-Side Driver With Fast and Equalized Switching Delay. IEEE J. Solid State Circuits 43(7): 1617-1625 (2008) - 2007
- [c2]Michael Wendt, Lenz Thoma, Bernhard Wicht, Doris Schmitt-Landsiedel:
A configurable High-Side/ low-Side Driver. ESSCIRC 2007: 256-259 - 2004
- [j2]Bernhard Wicht
Yield and speed optimization of a latch-type voltage sense amplifier. IEEE J. Solid State Circuits 39(7): 1148-1158 (2004) - 2003
- [c1]Bernhard Wicht
A yield-optimized latch-type SRAM sense amplifier. ESSCIRC 2003: 409-412 - 2001
- [j1]Bernhard Wicht
Analysis and compensation of the bitline multiplexer in SRAM current sense amplifiers. IEEE J. Solid State Circuits 36(11): 1745-1755 (2001)
Coauthor Index
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