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Shidhartha Das
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2020 – today
- 2022
- [j21]Amir Amirkhany
, Tanay Karnik, Shidhartha Das, Jun Deguchi, Yasuhiko Taito:
Introduction to the Special Section on the 2021 IEEE International Solid-State Circuits Conference (ISSCC). IEEE J. Solid State Circuits 57(1): 3-5 (2022) - [j20]Chuteng Zhou
ML-HW Co-Design of Noise-Robust TinyML Models and Always-On Analog Compute-in-Memory Edge Accelerator. IEEE Micro 42(6): 76-87 (2022) - [c45]Supreet Jeloka, Brian Cline, Shidhartha Das, Benoit Labbe, Alejandro Rico, Rainer Herberholz, Javier A. DeLaCruz, Rahul Mathur, Shawn Hung:
System technology co-optimization and design challenges for 3D IC. CICC 2022: 1-6 - [c44]Fernando García-Redondo
SACA: System-level Analog CIM Accelerators Simulation Framework: Accurate Simulation of Non-Ideal Components. DCIS 2022: 1-6 - [c43]Kanishkan Vadivel, Fernando García-Redondo
SACA: System-level Analog CIM Accelerators Simulation Framework: Architecture and Cycle-accurate System-to-device Simulator. DCIS 2022: 1-6 - 2021
- [j19]Zacharias Hadjilambrou
Harnessing CPU Electromagnetic Emanations for Resonance-Induced Voltage-Noise Characterization. IEEE Trans. Computers 70(9): 1338-1349 (2021) - [c42]Lingjun Zhu, Tuan Ta, Rossana Liu, Rahul Mathur
Power Delivery and Thermal-Aware Arm-Based Multi-Tier 3D Architecture. ISLPED 2021: 1-6 - [c41]Sanu Mathew, Shidhartha Das, Hugh Mair:
Session 4 Overview: Processors Digital Architectures and Systems Subcommittee. ISSCC 2021: 52-53 - [c40]Zhiyao Xie, Xiaoqing Xu, Matt Walker, Joshua Knebel, Kumaraguru Palaniswamy, Nicolas Hebert, Jiang Hu, Huanrui Yang, Yiran Chen
APOLLO: An Automated Power Modeling Framework for Runtime Power Introspection in High-Volume Commercial Microprocessors. MICRO 2021: 1-14 - [i5]George Papadimitriou, Manolis Kaliorakis, Athanasios Chatzidimitriou, Dimitris Gizopoulos, Greg Favor, Kumar Sankaran, Shidhartha Das:
A System-Level Voltage/Frequency Scaling Characterization Framework for Multicore CPUs. CoRR abs/2106.09975 (2021) - [i4]Chuteng Zhou, Fernando García-Redondo, Julian Büchel, Irem Boybat, Xavier Timoneda Comas, S. R. Nandakumar, Shidhartha Das, Abu Sebastian, Manuel Le Gallo, Paul N. Whatmough:
AnalogNets: ML-HW Co-Design of Noise-robust TinyML Models and Always-On Analog Compute-in-Memory Accelerator. CoRR abs/2111.06503 (2021) - 2020
- [j18]Benjamin J. Fletcher
A Spike-Latency Transceiver With Tunable Pulse Control for Low-Energy Wireless 3-D Integration. IEEE J. Solid State Circuits 55(9): 2414-2428 (2020) - [c39]Fernando García-Redondo
Training DNN IoT Applications for Deployment On Analog NVM Crossbars. IJCNN 2020: 1-8 - [c38]Benjamin J. Fletcher, Terrence S. T. Mak, Shidhartha Das:
A 3D-Stacked Cortex-M0 SoC with 20.3Gbps/mm2 7.1mW/mm2 Simultaneous Wireless Inter-Tier Data and Power Transfer. VLSI Circuits 2020: 1-2 - [i3]Saurabh Sinha, Xiaoqing Xu, Mudit Bhargava, Shidhartha Das, Brian Cline, Greg Yeric:
Stack up your chips: Betting on 3D integration to augment Moore's Law scaling. CoRR abs/2005.10866 (2020)
2010 – 2019
- 2019
- [j17]Benjamin J. Fletcher
Design and Optimization of Inductive-Coupling Links for 3-D-ICs. IEEE Trans. Very Large Scale Integr. Syst. 27(3): 711-723 (2019) - [j16]Kyungwook Chang
System-Level Power Delivery Network Analysis and Optimization for Monolithic 3-D ICs. IEEE Trans. Very Large Scale Integr. Syst. 27(4): 888-898 (2019) - [c37]Matthew Douthwaite, Fernando García-Redondo
A Time-Domain Current-Mode MAC Engine for Analogue Neural Networks in Flexible Electronics. BioCAS 2019: 1-4 - [c36]Said Hamdioui, Hoang Anh Du Nguyen, Mottaqiallah Taouil, Abu Sebastian
Applications of Computation-In-Memory Architectures based on Memristive Devices. DATE 2019: 486-491 - [c35]Benjamin J. Fletcher
CoDAPT: A Concurrent Data And Power Transceiver for Fully Wireless 3D-ICs. DATE 2019: 1343-1348 - [c34]Benjamin J. Fletcher
A 10.8pJ/bit Pulse-Position Inductive Transceiver for Low-Energy Wireless 3D Integration. ESSCIRC 2019: 121-124 - [c33]Vasileios Tenentes
Run-time Detection and Mitigation of Power-Noise Viruses. IOLTS 2019: 275-280 - [c32]Benjamin J. Fletcher
A Low-Energy Inductive Transceiver using Spike-Latency Encoding for Wireless 3D Integration. ISLPED 2019: 1-6 - [c31]Zacharias Hadjilambrou, Shidhartha Das, Paul N. Whatmough, David M. Bull, Yiannakis Sazeides:
GeST: An Automatic Framework For Generating CPU Stress-Tests. ISPASS 2019: 1-10 - [i2]Sergey Mileiko, Thanasin Bunnam, Fei Xia, Rishad A. Shafik, Alex Yakovlev, Shidhartha Das:
Neural Network Design for Energy-Autonomous AI Applications using Temporal Encoding. CoRR abs/1910.07492 (2019) - [i1]Fernando García-Redondo, Shidhartha Das, Glen Rosendale:
Training DNN IoT Applications for Deployment On Analog NVM Crossbars. CoRR abs/1910.13850 (2019) - 2018
- [j15]Zacharias Hadjilambrou
Sensing CPU Voltage Noise Through Electromagnetic Emanations. IEEE Comput. Archit. Lett. 17(1): 68-71 (2018) - [j14]Issa Qiqieh
Significance-Driven Logic Compression for Energy-Efficient Multiplier Design. IEEE J. Emerg. Sel. Topics Circuits Syst. 8(3): 417-430 (2018) - [j13]Andrea Bevilacqua
Guest Editorial Special Issue on the 47th European Solid-State Circuits Conference (ESSCIRC). IEEE J. Solid State Circuits 53(7): 1876-1877 (2018) - [j12]Rishad A. Shafik, Alex Yakovlev
Real-Power Computing. IEEE Trans. Computers 67(10): 1445-1461 (2018) - [c30]Benjamin J. Fletcher
A high-speed design methodology for inductive coupling links in 3D-ICs. DATE 2018: 497-502 - [c29]Georgios Karakonstantis, Konstantinos Tovletoglou
An energy-efficient and error-resilient server ecosystem exceeding conservative scaling limits. DATE 2018: 1099-1104 - [c28]Benjamin J. Fletcher
Low-power 3D integration using inductive coupling links for neurotechnology applications. DATE 2018: 1211-1216 - [c27]Konstantinos Tovletoglou
Measuring and Exploiting Guardbands of Server-Grade ARMv8 CPU Cores and DRAMs. DSN Workshops 2018: 6-9 - [c26]Zacharias Hadjilambrou, Shidhartha Das, Marco A. Antoniades
Leveraging CPU Electromagnetic Emanations for Voltage Noise Characterization. MICRO 2018: 573-585 - [c25]Emre Ozer, Balaji Venu, Xabier Iturbe
Error Correlation Prediction in Lockstep Processors for Safety-Critical Systems. MICRO 2018: 737-748 - 2017
- [j11]Georgios Karakonstantis, Dimitrios S. Nikolopoulos
Error-Resilient Server Ecosystems for Edge and Cloud Datacenters. Computer 50(12): 78-81 (2017) - [j10]Paul N. Whatmough
Power Integrity Analysis of a 28 nm Dual-Core ARM Cortex-A57 Cluster Using an All-Digital Power Delivery Monitor. IEEE J. Solid State Circuits 52(6): 1643-1654 (2017) - [c24]Dave Burke, Dainius Jenkus, Issa Qiqieh
Significance-driven adaptive approximate computing for energy-efficient image processing applications: special session paper. CODES+ISSS 2017: 28:1-28:2 - [c23]Vasileios Tenentes
Hardware and software innovations in energy-efficient system-reliability monitoring. DFT 2017: 1-5 - [c22]Kyungwook Chang, Shidhartha Das, Saurabh Sinha, Brian Cline, Greg Yeric, Sung Kyu Lim
Frequency and time domain analysis of power delivery network for monolithic 3D ICs. ISLPED 2017: 1-6 - [c21]George Papadimitriou, Manolis Kaliorakis, Athanasios Chatzidimitriou, Dimitris Gizopoulos, Peter Lawthers, Shidhartha Das:
Harnessing voltage margins for energy efficiency in multicore CPUs. MICRO 2017: 503-516 - [c20]Issa Qiqieh
Energy-efficient approximate wallace-tree multiplier using significance-driven logic compression. SiPS 2017: 1-6 - 2016
- [j9]Robert C. Aitken, Vikas Chandra, Brian Cline, Shidhartha Das, David Pietromonaco, Lucian Shifren, Saurabh Sinha, Greg Yeric:
Predicting future complementary metal-oxide-semiconductor technology - challenges and approaches. IET Comput. Digit. Tech. 10(6): 315-322 (2016) - [c19]Xabier Iturbe
A Triple Core Lock-Step (TCLS) ARM® Cortex®-R5 Processor for Safety-Critical and Ultra-Reliable Applications. DSN Workshops 2016: 246-249 - 2015
- [c18]Paul N. Whatmough, Shidhartha Das, David M. Bull:
Analysis of adaptive clocking technique for resonant supply voltage noise mitigation. ISLPED 2015: 128-133 - [c17]Shidhartha Das, Paul N. Whatmough, David M. Bull:
Modeling and characterization of the system-level Power Delivery Network for a dual-core ARM Cortex-A57 cluster in 28nm CMOS. ISLPED 2015: 146-151 - [c16]Paul N. Whatmough, Shidhartha Das, Zacharias Hadjilambrou, David M. Bull:
14.6 An all-digital power-delivery monitor for analysis of a 28nm dual-core ARM Cortex-A57 cluster. ISSCC 2015: 1-3 - [c15]Paul N. Whatmough, George Smart, Shidhartha Das, Yiannis Andreopoulos, David M. Bull:
A 0.6V all-digital body-coupled wakeup transceiver for IoT applications. VLSIC 2015: 98- - 2014
- [j8]Paul N. Whatmough, Shidhartha Das, David M. Bull:
A Low-Power 1-GHz Razor FIR Accelerator With Time-Borrow Tracking Pipeline and Approximate Error Correction in 65-nm CMOS. IEEE J. Solid State Circuits 49(1): 84-94 (2014) - [j7]Shidhartha Das, Ganesh S. Dasika, Karthik Shivashankar, David M. Bull:
A 1 GHz Hardware Loop-Accelerator With Razor-Based Dynamic Adaptation for Energy-Efficient Operation. IEEE Trans. Circuits Syst. I Regul. Pap. 61-I(8): 2290-2298 (2014) - 2013
- [j6]Paul N. Whatmough, Shidhartha Das, David M. Bull, Izzat Darwazeh:
Circuit-Level Timing Error Tolerance for Low-Power DSP Filters and Transforms. IEEE Trans. Very Large Scale Integr. Syst. 21(6): 989-999 (2013) - [c14]Shidhartha Das, Ganesh S. Dasika, Karthik Shivashankar, David M. Bull:
A 1GHz hardware loop-accelerator with razor-based dynamic adaptation for energy-efficient operation. CICC 2013: 1-4 - [c13]Paul N. Whatmough, Shidhartha Das, David M. Bull:
A low-power 1GHz razor FIR accelerator with time-borrow tracking pipeline and approximate error correction in 65nm CMOS. ISSCC 2013: 428-429 - 2012
- [c12]Paul N. Whatmough, Shidhartha Das, David M. Bull, Izzat Darwazeh:
Selective time borrowing for DSP pipelines with hybrid voltage control loop. ASP-DAC 2012: 763-768 - 2011
- [j5]David M. Bull, Shidhartha Das, Karthik Shivashankar, Ganesh S. Dasika, Krisztián Flautner, David T. Blaauw:
A Power-Efficient 32 bit ARM Processor Using Timing-Error Detection and Correction for Transient-Error Tolerance and Adaptation to PVT Variation. IEEE J. Solid State Circuits 46(1): 18-31 (2011) - [j4]David M. Bull, Shidhartha Das, Karthik Shivashankar, Ganesh S. Dasika, Krisztián Flautner, David T. Blaauw:
Correction to "A Power-Efficient 32 bit ARM Processor Using Timing-Error Detection and Correction for Transient-Error Tolerance and Adaptation to PVT Variation". IEEE J. Solid State Circuits 46(3): 705 (2011) - [c11]Paul N. Whatmough, Shidhartha Das, David M. Bull, Izzat Darwazeh:
Error-resilient low-power DSP via path-delay shaping. DAC 2011: 1008-1013 - 2010
- [c10]Paul N. Whatmough, Izzat Darwazeh, David M. Bull, Shidhartha Das, Danny Kershaw:
A robust FIR filter with in situ error detection. ISCAS 2010: 4185-4188 - [c9]David M. Bull, Shidhartha Das, Karthik Shivashankar, Ganesh S. Dasika, Krisztián Flautner, David T. Blaauw:
A power-efficient 32b ARM ISA processor using timing-error detection and correction for transient-error tolerance and adaptation to PVT variation. ISSCC 2010: 284-285
2000 – 2009
- 2009
- [b1]Shidhartha Das:
Razor: A Variability-Tolerant Design Methodology for Low-Power and Robust Computing. University of Michigan, USA, 2009 - [j3]Shidhartha Das, Carlos Tokunaga
RazorII: In Situ Error Detection and Correction for PVT and SER Tolerance. IEEE J. Solid State Circuits 44(1): 32-48 (2009) - [c8]Shidhartha Das, David T. Blaauw, David M. Bull, Krisztián Flautner, Rob Aitken:
Addressing design margins through error-tolerant circuits. DAC 2009: 11-12 - [c7]Shidhartha Das, David T. Blaauw:
Adaptive Design for Nanometer Technology. ISCAS 2009: 77-80 - 2008
- [c6]Ganesh S. Dasika, Shidhartha Das, Kevin Fan, Scott A. Mahlke, David M. Bull:
DVFS in loop accelerators using BLADES. DAC 2008: 894-897 - [c5]David T. Blaauw, Sudherssen Kalaiselvan, Kevin Lai, Wei-Hsiang Ma, Sanjay Pant, Carlos Tokunaga
Razor II: In Situ Error Detection and Correction for PVT and SER Tolerance. ISSCC 2008: 400-401 - 2006
- [j2]Shidhartha Das, David Roberts, Seokwoo Lee, Sanjay Pant, David T. Blaauw, Todd M. Austin, Krisztián Flautner, Trevor N. Mudge:
A self-tuning DVS processor using delay-error detection and correction. IEEE J. Solid State Circuits 41(4): 792-804 (2006) - 2004
- [j1]Dan Ernst, Shidhartha Das, Seokwoo Lee, David T. Blaauw, Todd M. Austin, Trevor N. Mudge, Nam Sung Kim, Krisztián Flautner:
Razor: Circuit-Level Correction of Timing Errors for Low-Power Operation. IEEE Micro 24(6): 10-20 (2004) - [c4]Seokwoo Lee, Shidhartha Das, Valeria Bertacco, Todd M. Austin, David T. Blaauw, Trevor N. Mudge:
Circuit-aware architectural simulation. DAC 2004: 305-310 - [c3]Seokwoo Lee, Shidhartha Das, Toan Pham, Todd M. Austin, David T. Blaauw, Trevor N. Mudge:
Reducing pipeline energy demands with local DVS and dynamic retiming. ISLPED 2004: 319-324 - 2003
- [c2]Shidhartha Das, Kanak Agarwal, David T. Blaauw, Dennis Sylvester:
Optimal Inductance for On-chip RLC Interconnections. ICCD 2003: 264- - [c1]Dan Ernst, Nam Sung Kim, Shidhartha Das, Sanjay Pant, Rajeev R. Rao, Toan Pham, Conrad H. Ziesler, David T. Blaauw, Todd M. Austin, Krisztián Flautner, Trevor N. Mudge:
Razor: A Low-Power Pipeline Based on Circuit-Level Timing Speculation. MICRO 2003: 7-18
Coauthor Index
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