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Edith Beigné
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2020 – today
- 2024
- [j26]Huseyin Ekin Sumbul
, Jae-sun Seo
A Fully Digital and Row-Pipelined Compute-in-Memory Neural Network Accelerator With System-on-Chip-Level Benchmarking for Augmented/Virtual Reality Applications. IEEE Micro 44(2): 61-70 (2024) - [c76]Tony F. Wu, Huichu Liu, Huseyin Ekin Sumbul, Lita Yang, Dipti Baheti, Jeremy Coriell, William Koven, Anu Krishnan, Mohit Mittal, Matheus Trevisan Moreira, Max Waugaman, Laurent Ye, Edith Beigné:
11.2 A 3D integrated Prototype System-on-Chip for Augmented Reality Applications Using Face-to-Face Wafer Bonded 7nm Logic at <2μm Pitch with up to 40% Energy Reduction at Iso-Area Footprint. ISSCC 2024: 210-212 - 2023
- [c75]Matheus Trevisan Moreira, William Koven, Tony F. Wu, Huseyin Ekin Sumbul, Edith Beigné:
A QDI Interconnect for 3D Systems Using Industry Standard EDA and Cell Libraries. ASYNC 2023: 58-59 - [c74]Karl Kaiser, Dinesh Patil, Edith Beigné:
A prototype 5nm custom sensor SoC for Augmented Reality/Virtual Reality targeting Smartglasses with embedded computer vision, audio, security and ML. VLSI Technology and Circuits 2023: 1-2 - 2022
- [j25]Lita Yang
Three-Dimensional Stacked Neural Network Accelerator Architectures for AR/VR Applications. IEEE Micro 42(6): 116-124 (2022) - [c73]Huseyin Ekin Sumbul
System-Level Design and Integration of a Prototype AR/VR Hardware Featuring a Custom Low-Power DNN Accelerator Chip in 7nm Technology for Codec Avatars. CICC 2022: 1-8 - [c72]Linyan Mei, Huichu Liu, Tony F. Wu, Huseyin Ekin Sumbul, Marian Verhelst
A Uniform Latency Model for DNN Accelerators with Diverse Architectures and Dataflows. DATE 2022: 220-225 - [c71]Daniel H. Morris, Huichu Liu, Tony F. Wu, Huseyin Ekin Sumbul, Elnaz Ansari, Alexandre Barachant, Jonathan Reid, Edith Beigné:
Co-Optimization of SRAM Circuits with Sequential Access Patterns in a 7nm SoC Achieving 58% Memory Energy Reduction for AR Applications. VLSI Technology and Circuits 2022: 216-217 - 2021
- [c70]Tony F. Wu, Doyun Kim, Daniel H. Morris, Edith Beigné:
Evaluation of Low-Voltage SRAM for Error-Resilient Augmented Reality Applications. SiPS 2021: 1-3 - 2020
- [c69]Ivan Miro Panades, Benoît Tain
SamurAI: A 1.7MOPS-36GOPS Adaptive Versatile IoT Node with 15, 000× Peak-to-Idle Power Reduction, 207ns Wake-Up Time and 1.3TOPS/W ML Efficiency. VLSI Circuits 2020: 1-2 - [i1]Maxence Bouvier, Alexandre Valentian, Thomas Mesquida, François Rummens, Marina Reyboz, Elisa Vianello, Edith Beigné:
Spiking Neural Networks Hardware Implementations and Challenges: a Survey. CoRR abs/2005.01467 (2020)
2010 – 2019
- 2019
- [j24]Maxence Bouvier
Spiking Neural Networks Hardware Implementations and Challenges: A Survey. ACM J. Emerg. Technol. Comput. Syst. 15(2): 22:1-22:35 (2019) - [j23]Laurent Millet
A 5500-frames/s 85-GOPS/W 3-D Stacked BSI Vision Chip Based on Parallel In-Focal-Plane Acquisition and Processing. IEEE J. Solid State Circuits 54(4): 1096-1105 (2019) - [j22]Daniele Jahier Pagliari
Fine-Grain Back Biasing for the Design of Energy-Quality Scalable Operators. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38(6): 1042-1055 (2019) - [c68]Imed Jani, Didier Lattard, Pascal Vivet, Lucile Arnaud, Edith Beigné:
Misalignment Analysis and Electrical Performance of High Density 3D-IC interconnects. 3DIC 2019: 1-4 - [c67]Sung-Gun Cho, Edith Beigné, Zhengya Zhang
A 2048-Neuron Spiking Neural Network Accelerator With Neuro-Inspired Pruning And Asynchronous Network On Chip In 40nm CMOS. CICC 2019: 1-4 - [c66]Imed Jani, Didier Lattard, Pascal Vivet
Test Solutions for High Density 3D-IC Interconnects - Focus on SRAM-on-Logic Partitioning. ETS 2019: 1-2 - [c65]Tony F. Wu, Binh Q. Le, Robert M. Radway
A 43pJ/Cycle Non-Volatile Microcontroller with 4.7μs Shutdown/Wake-up Integrating 2.3-bit/Cell Resistive RAM and Resilience Techniques. ISSCC 2019: 226-228 - [c64]Roman Gauchi
Memory Sizing of a Scalable SRAM In-Memory Computing Tile Based Architecture. VLSI-SoC 2019: 166-171 - 2018
- [c63]Edith Beigné:
FDSOI Circuit Design for High Energy Efficiency: Wide Operating Range and ULP Applications - a 7-Year Experience. ESSCIRC 2018: 216 - [c62]Edith Beigné:
FDSOI circuit design for high energy efficiency: Wide operating range and ULP applications - a 7-year experience. ESSDERC 2018: 156 - [c61]Imed Jani, Didier Lattard, Pascal Vivet
BISTs for post-bond test and electrical analysis of high density 3D interconnect defects. ETS 2018: 1-6 - [c60]Pascal Vivet
Monolithic 3D: an alternative to advanced CMOS scaling, technology perspectives and associated design methodology challenges. ICECS 2018: 157-160 - [c59]Mickael Maman, Dominique Morche, Baudouin Martineau
Benefits of Joint Optimization of Tunable Wake-up Radio Architecture and Protocols. ICECS 2018: 789-792 - [c58]Dusan M. Stipanovic
Some Local Stability Properties of an Autonomous Long Short-Term Memory Neural Network Model. ISCAS 2018: 1-5 - [c57]Youngmin Shin, Phillip J. Restle, Edith Beigné:
Session 7 overview: Neuromorphic, clocking and security circuits: Digital circuits subcommittee. ISSCC 2018: 116-117 - [c56]Dennis Sylvester, Koji Hirairi, Edith Beigné:
Session 18 overview: Adaptive circuits and digital regulators: Digital circuit techniques subcommittee. ISSCC 2018: 298-299 - [c55]Anthony Quelen, Gaël Pillonnet
A 2.5μW 0.0067mm2 automatic back-biasing compensation unit achieving 50% leakage reduction in FDSOI 28nm over 0.35-to-1V VDD range. ISSCC 2018: 304-306 - [c54]Reda Boumchedda, Jean-Philippe Noel, Bastien Giraud, Adam Makosiej, Marco Antonio Rios, Eduardo Esmanhotto, Emilien Bourde-Cicé, Mathis Bellet, David Turgis, Edith Beigné:
Energy-Efficient 4T SRAM Bitcell with 2T Read-Port for Ultra-Low-Voltage Operations in 28 nm 3D Monolithic CoolCubeTM Technology. NANOARCH 2018: 131-137 - [c53]Laurent Millet, Stéphane Chevobbe
A 5500FPS 85GOPS/W 3D Stacked BSI Vision Chip Based on Parallel in-Focal-Plane Acquisition and Processing. VLSI Circuits 2018: 245-246 - 2017
- [j21]Marc Belleville, Anca Molnos, Gilles Sicard, Jean-Frédéric Christmann, Dominique Morche, Duy-Hieu Bui
Adaptive Architectures, Circuits and Technology Solutions for Future IoT Systems. J. Low Power Electron. 13(3): 298-309 (2017) - [j20]Pascal Vivet
A 4 × 4 × 2 Homogeneous Scalable 3D Network-on-Chip Circuit With 326 MFlit/s 0.66 pJ/b Robust and Fault Tolerant Asynchronous 3D Links. IEEE J. Solid State Circuits 52(1): 33-49 (2017) - [j19]Davide Rossi, Antonio Pullini, Igor Loi, Michael Gautschi, Frank Kagan Gürkaynak, Adam Teman
Energy-Efficient Near-Threshold Parallel Computing: The PULPv2 Cluster. IEEE Micro 37(5): 20-31 (2017) - [j18]Anuj Grover
A 32 kb 0.35-1.2 V, 50 MHz-2.5 GHz Bit-Interleaved SRAM With 8 T SRAM Cell and Data Dependent Write Assist in 28-nm UTBB-FDSOI CMOS. IEEE Trans. Circuits Syst. I Regul. Pap. 64-I(9): 2438-2447 (2017) - [j17]Reda Boumchedda
High-Density 4T SRAM Bitcell in 14-nm 3-D CoolCube Technology Exploiting Assist Techniques. IEEE Trans. Very Large Scale Integr. Syst. 25(8): 2296-2306 (2017) - [j16]Duy-Hieu Bui
AES Datapath Optimization Strategies for Low-Power Low-Energy Multisecurity-Level Internet-of-Things Applications. IEEE Trans. Very Large Scale Integr. Syst. 25(12): 3281-3290 (2017) - [c52]Daniele Jahier Pagliari
A methodology for the design of dynamic accuracy operators by runtime back bias. DATE 2017: 1165-1170 - [c51]Laurent Alacoque
A 128x128, 34μm pitch, 8.9mW, 190mK NETD, TECless Uncooled IR bolometer image sensor with column-wise processing. IMSE 2017: 68-73 - [c50]Ivan Miro Panades, Edith Beigné
In-situ Fmax/Vmin tracking for energy efficiency and reliability optimization. IOLTS 2017: 96-99 - [c49]Yasuhisa Shimazaki, John Maneatis, Edith Beigné:
Session 8 overview: Digital PLLs and security circuits. ISSCC 2017: 140-141 - [c48]Atsuki Inoue, Dennis Sylvester, Edith Beigné:
Session 20 overview: Digital voltage regulators and low-power techniques. ISSCC 2017: 334-335 - [c47]Kathy Wilcox, Youngmin Shin, Edith Beigné:
Session 26 overview: Processor-power management and clocking. ISSCC 2017: 436-437 - [c46]Imed Jani, Didier Lattard, Pascal Vivet
Innovative structures to test bonding alignment and characterize high density interconnects in 3D-IC. NEWCAS 2017: 153-156 - [c45]Thomas Mesquida, Alexandre Valentian, David Bol, Edith Beigné
Architecture exploration of a fixed point computation unit using precise timing spiking neurons. PATMOS 2017: 1-8 - 2016
- [j15]Edith Beigné
Introduction to the January Special Issue on the 2015 IEEE International Solid-State Circuits Conference. IEEE J. Solid State Circuits 51(1): 3-7 (2016) - [c44]Davide Rossi
193 MOPS/mW @ 162 MOPS, 0.32V to 1.15V voltage range multi-core accelerator for energy efficient parallel and sequential digital processing. COOL Chips 2016: 1-3 - [c43]Duy-Hieu Bui
Ultra low-power and low-energy 32-bit datapath AES architecture for IoT applications. ICICDT 2016: 1-4 - [c42]Pascal Vivet
8.1 A 4×4×2 homogeneous scalable 3D network-on-chip circuit with 326MFlit/s 0.66pJ/b robust and fault-tolerant asynchronous 3D links. ISSCC 2016: 146-147 - [c41]Pierre-Emmanuel Gaillardon, Romain Magni, Luca Gaetano Amarù, Mehdi Hasan, Ross Walker, Berardi Sensale Rodriguez, Jean-Frédéric Christmann, Edith Beigné
Three-Independent-Gate Transistors: Opportunities in digital, analog and RF applications. LATS 2016: 195-200 - [c40]Maurício Altieri, Suzanne Lesecq, Edith Beigné
Tracking BTI and HCI effects at circuit-level in adaptive systems. NEWCAS 2016: 1-4 - 2015
- [j14]Pierre-Emmanuel Gaillardon, Edith Beigné
A Survey on Low-Power Techniques with Emerging Technologies: From Devices to Systems. ACM J. Emerg. Technol. Comput. Syst. 12(2): 12:1-12:26 (2015) - [j13]Edith Beigné
A 460 MHz at 397 mV, 2.6 GHz at 1.3 V, 32 bits VLIW DSP Embedding F MAX Tracking. IEEE J. Solid State Circuits 50(1): 125-136 (2015) - [c39]Eldar Zianbetov, Edith Beigné
Non-volatility for Ultra-Low Power Asynchronous Circuits in Hybrid CMOS/Magnetic Technology. ASYNC 2015: 139-146 - [c38]Edith Beigné
Ultra-low power volatile and non-volatile asynchronous circuits using back-biasing. ECCTD 2015: 1-4 - [c37]Edith Beigné
UTBB FDSOI technology flexibility for ultra low power internet-of-things applications. ESSDERC 2015: 164-167 - [c36]Edith Beigné
Fine-grain DVFS and AVFS techniques for complex SoC design: An overview of architectural solutions through technology nodes. ISCAS 2015: 1550-1553 - [c35]Jeremy Lopes, Gregory di Pendina
Radiative Effects on MRAM-Based Non-Volatile Elementary Structures. ISVLSI 2015: 321-326 - [c34]Florent Berthier, Edith Beigné
Power gain estimation of an event-driven wake-up controller dedicated to WSN's microcontroller. NEWCAS 2015: 1-4 - [c33]Soundous Chairat, Edith Beigné
Dedicated network for distributed configuration in a mixed-signal Wireless Sensor Node circuit. PATMOS 2015: 55-62 - [c32]Emilie Garat, David Coriat, Edith Beigné
Unified Power Format (UPF) methodology in a vendor independent flow. PATMOS 2015: 82-88 - [c31]Maurício Altieri, Suzanne Lesecq, Diego Puschini, Olivier Héron, Edith Beigné
Evaluation and mitigation of aging effects on a digital on-chip voltage and temperature sensor. PATMOS 2015: 111-117 - 2014
- [j12]Ivan Miro Panades, Edith Beigné
A Fine-Grain Variation-Aware Dynamic Vdd-Hopping AVFS Architecture on a 32 nm GALS MPSoC. IEEE J. Solid State Circuits 49(7): 1475-1486 (2014) - [j11]Lionel Vincent, Edith Beigné
Dynamic Variability Monitoring Using Statistical Tests for Energy Efficient Adaptive Architectures. IEEE Trans. Circuits Syst. I Regul. Pap. 61-I(6): 1741-1754 (2014) - [c30]Ngoc-Mai Nguyen, Edith Beigné
H.264/AVC hardware encoders and low-power features. APCCAS 2014: 77-80 - [c29]Yeter Akgul, Diego Puschini, Suzanne Lesecq, Edith Beigné
Power management through DVFS and dynamic body biasing in FD-SOI circuits. DAC 2014: 183:1-183:6 - [c28]Ngoc-Mai Nguyen, Warody Lombardi, Edith Beigné
FIFO-level-based power management and its application to an H.264 encoder. IECON 2014: 158-163 - [c27]Robin Wilson, Edith Beigné
27.1 A 460MHz at 397mV, 2.6GHz at 1.3V, 32b VLIW DSP, embedding FMAX tracking. ISSCC 2014: 452-453 - 2013
- [c26]Sylvain Durand, Suzanne Lesecq, Edith Beigné, Diego Puschini:
Event-based DVFS control in GALS-ANoC MPSoCs. ACC 2013: 5074-5079 - [c25]Jérémie Hamon, Edith Beigné
Automatic Leakage Control for Wide Range Performance QDI Asynchronous Circuits in FD-SOI Technology. ASYNC 2013: 142-149 - [c24]Edith Beigné, Alexandre Valentian, Bastien Giraud, Olivier Thomas, Thomas Benoist, Yvain Thonnart, Serge Bernard, Guillaume Moritz, Olivier Billoint, Y. Maneglia, Philippe Flatresse, Jean-Philippe Noel, Fady Abouzeid
Ultra-wide voltage range designs in fully-depleted silicon-on-insulator FETs. DATE 2013: 613-618 - [c23]Smriti Joshi, Anne Lombardot, Marc Belleville, Edith Beigné, Stéphane Girard
A gate level methodology for efficient statistical leakage estimation in complex 32nm circuits. DATE 2013: 1056-1057 - [c22]Edith Beigné
A fine grain variation-aware dynamic Vdd-hopping AVFS architecture on a 32nm GALS MPSoC. ESSCIRC 2013: 57-60 - [c21]Yeter Akgul, Diego Puschini, Suzanne Lesecq, Edith Beigné
Methodology for Power Mode selection in FD-SOI circuits with DVFS and Dynamic Body Biasing. PATMOS 2013: 199-206 - [c20]Bertrand Pelloux-Prayer, Alexandre Valentian, Bastien Giraud, Yvain Thonnart
Fine grain multi-VT co-integration methodology in UTBB FD-SOI technology. VLSI-SoC 2013: 168-173 - 2012
- [j10]Smriti Joshi, Anne Lombardot, Philippe Flatresse, Carmelo D'Agostino
Statistical Estimation of Dominant Physical Parameters for Leakage Variability in 32 Nanometer CMOS, Under Supply Voltage Variations. J. Low Power Electron. 8(1): 113-124 (2012) - [c19]Lionel Vincent, Suzanne Lesecq, Philippe Maurine, Edith Beigné
Local Condition Monitoring in integrated circuits using a set of Kolmogorov-Smirnov tests. CCA 2012: 646-651 - [c18]Yvain Thonnart
A Pseudo-Synchronous Implementation Flow for WCHB QDI Asynchronous Circuits. ASYNC 2012: 73-80 - [c17]Lionel Vincent, Philippe Maurine, Suzanne Lesecq, Edith Beigné
Embedding statistical tests for on-chip dynamic voltage and temperature monitoring. DAC 2012: 994-999 - [c16]Jean-Frédéric Christmann, Edith Beigné
Energy harvesting and power management for autonomous sensor nodes. DAC 2012: 1049-1054 - [c15]Jean-Frédéric Christmann, Edith Beigné
Event-driven asynchronous voltage monitoring in energy harvesting platforms. NEWCAS 2012: 457-460 - 2011
- [j9]Jean-Frédéric Christmann, Edith Beigné
Bringing Robustness and Power Efficiency to Autonomous Energy-Harvesting Microsystems. IEEE Des. Test Comput. 28(5): 84-94 (2011) - [j8]Pascal Vivet
On-line Power Optimization of Data Flow Multi-Core Architecture Based on Vdd-Hopping for Local Dynamic Voltage and Frequency Scaling. J. Low Power Electron. 7(2): 265-273 (2011) - [j7]Carolina Albea
Architecture and Robust Control of a Digital Frequency-Locked Loop for Fine-Grain Dynamic Voltage and Frequency Scaling in Globally Asynchronous Locally Synchronous Structures. J. Low Power Electron. 7(3): 328-340 (2011) - [j6]Bettina Rebaud, Marc Belleville, Edith Beigné
Timing slack monitoring under process and environmental variations: Application to a DSP performance optimization. Microelectron. J. 42(5): 718-732 (2011) - [c14]Sylvain Durand, Suzanne Lesecq, Edith Beigné, Christian Fabre
Low-Cost Dynamic Voltage and Frequency Management Based upon Robust Control Techniques under Thermal Constraints. FMCO 2011: 334-353 - 2010
- [j5]Motoi Ichihashi, Hélène Lhermet, Edith Beigné
An On-Chip Multi-Mode Buck DC-DC Converter for Fine-Grain DVS on a Multi-Power Domain SoC Using a 65-nm Standard CMOS Logic Process. J. Low Power Electron. 6(1): 201-210 (2010) - [c13]Jean-Frédéric Christmann, Edith Beigné
Bringing Robustness and Power Efficiency to Autonomous Energy Harvesting Microsystems. ASYNC 2010: 62-71 - [c12]Pascal Vivet
On Line Power Optimization of Data Flow Multi-core Architecture Based on Vdd-Hopping for Local DVFS. PATMOS 2010: 94-104
2000 – 2009
- 2009
- [j4]Edith Beigné
An Asynchronous Power Aware and Adaptive NoC Based Circuit. IEEE J. Solid State Circuits 44(4): 1167-1177 (2009) - [j3]Yvain Thonnart
Power Reduction of Asynchronous Logic Circuits Using Activity Detection. IEEE Trans. Very Large Scale Integr. Syst. 17(7): 893-906 (2009) - [c11]Yvain Thonnart
Design and Implementation of a GALS Adapter for ANoC Based Architectures. ASYNC 2009: 13-22 - [c10]Bettina Rebaud, Marc Belleville, Edith Beigné
Digital Timing Slack Monitors and Their Specific Insertion Flow for Adaptive Compensation of Variabilities. PATMOS 2009: 266-275 - [c9]Motoi Ichihashi, Hélène Lhermet, Edith Beigné
An On-Chip Multi-mode Buck DC-DC Converter for Fine-Grain DVS on a Multi-power Domain SoC Using a 65-nm Standard CMOS Logic Process. PATMOS 2009: 336-346 - 2008
- [j2]Didier Lattard, Edith Beigné
A Reconfigurable Baseband Platform Based on an Asynchronous Network-on-Chip. IEEE J. Solid State Circuits 43(1): 223-235 (2008) - [j1]Alexandre Valentian, Edith Beigné
Automatic Gate Biasing of an SCCMOS Power Switch Achieving Maximum Leakage Reduction and Lowering Leakage Current Variability. IEEE J. Solid State Circuits 43(7): 1688-1698 (2008) - [c8]Yvain Thonnart
Automatic Power Regulation Based on an Asynchronous Activity Detection and its Application to ANOC Node Leakage Reduction. ASYNC 2008: 48-57 - [c7]Edith Beigné
A fully integrated power supply unit for fine grain power management application to embedded Low Voltage SRAMs. ESSCIRC 2008: 138-141 - [c6]Edith Beigné, Fabien Clermidy, Sylvain Miermont, Pascal Vivet:
Dynamic Voltage and Frequency Scaling Architecture for Units Integration within a GALS NoC. NOCS 2008: 129-138 - 2007
- [c5]Alexandre Valentian, Edith Beigné
Gate bias circuit for an SCCMOS power switch achieving maximum leakage reduction. ESSCIRC 2007: 300-303 - [c4]Didier Lattard, Edith Beigné
A Telecom Baseband Circuit based on an Asynchronous Network-on-Chip. ISSCC 2007: 258-601 - 2006
- [c3]D. Caucheteux, Edith Beigné
AsyncRFID: Fully Asynchronous Contactless Systems, Providing High Data Rates, Low Power and Dynamic Adaptation. ASYNC 2006: 86-97 - [c2]Edith Beigné
Design of On-chip and Off-chip Interfaces for a GALS NoC Architecture. ASYNC 2006: 172-183 - 2005
- [c1]Edith Beigné
An Asynchronous NOC Architecture Providing Low Latency Service and Its Multi-Level Design Framework. ASYNC 2005: 54-63
Coauthor Index
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