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20th ASP-DAC 2015: Chiba, Japan
- The 20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015, Chiba, Japan, January 19-22, 2015. IEEE 2015, ISBN 978-1-4799-7792-5
- Udo Wolz:
The required technologies for Automotive towards 2020. 1 - Dongsheng Yang, Wei Deng, Tomohiro Ueno, Teerachot Siriburanon
, Satoshi Kondo, Kenichi Okada
An HDL-synthesized gated-edge-injection PLL with a current output DAC. 2-3 - Takehiko Amaki, Masanori Hashimoto
An oscillator-based true random number generator with process and temperature tolerance. 4-5 - Takanori Machida, Dai Yamamoto, Mitsugu Iwamoto, Kazuo Sakiyama:
Implementation of double arbiter PUF and its performance evaluation on FPGA. 6-7 - Yohei Umeki, Koji Yanagida, Shusuke Yoshimoto, Shintaro Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi
A negative-resistance sense amplifier for low-voltage operating STT-MRAM. 8-9 - Nobuaki Kobayashi, Ryusuke Ito, Tadayoshi Enomoto:
A high stability, low supply voltage and low standby power six-transistor CMOS SRAM. 10-11 - Xuan-Thuan Nguyen, Cong-Kha Pham
An efficient multi-port memory controller for multimedia applications. 12-13 - Masanori Hashimoto
Reliability-configurable mixed-grained reconfigurable array compatible with high-level synthesis. 14-15 - Yozaburo Nakai, Shintaro Izumi, Ken Yamashita, Masanao Nakano, Hiroshi Kawaguchi
A 14µA ECG processor with noise tolerant heart rate extractor and FeRAM for wearable healthcare systems. 16-17 - Xiaowei Ren, Qihang Yu, Badong Chen, Nanning Zheng, Pengju Ren:
A 128-way FPGA platform for the acceleration of KLMS algorithm. 18-19 - Xiaowei Ren, Qihang Yu, Badong Chen, Nanning Zheng, Pengju Ren:
A real-time permutation entropy computation for EEG signals. 20-21 - Jiang Yu, Geng Liu, Xin Zhang, Pengju Ren:
A high efficient hardware architecture for multiview 3DTV. 22-23 - Hsiao-Wei Chien, Jyun-Long Lai, Chao-Chieh Wu, Chih-Tsun Huang, Ting-Shuo Hsu, Jing-Jia Liou:
Design of a scalable many-core processor for embedded applications. 24-25 - Daisuke Fujimoto, Noriyuki Miura, Yu-ichi Hayashi, Naofumi Homma, Takafumi Aoki, Makoto Nagata
A DPA/DEMA/LEMA-resistant AES cryptographic processor with supply-current equalizer and micro EM probe sensor. 26-27 - Xiwei Huang, Jing Guo, Mei Yan, Hao Yu:
A 64×64 1200fps dual-mode CMOS ion-image sensor for accurate DNA sequencing. 28-29 - Toshihiro Ozaki, Tetsuya Hirose, Takahiro Nagai, Keishi Tsubaki, Nobutaka Kuroki, Masahiro Numa:
A 0.21-V minimum input, 73.6% maximum efficiency, fully integrated 3-terminal voltage converter with MPPT for low-voltage energy harvesters. 30-31 - Junki Hashiba, Toru Kawajiri, Yuya Hasegawa, Hiroki Ishikuro:
Dual-output wireless power delivery system for small size large volume wireless memory card. 32-33 - Daisuke Kanemoto, Keigo Oshiro, Keiji Yoshida, Haruichi Kanaya:
A tri-level 50MS/s 10-bit capacitive-DAC for Bluetooth applications. 34-35 - Aravind Tharayil Narayanan
A tail-current modulated VCO with adaptive-bias scheme. 36-37 - Jili Zhang, Chenluan Wang, Shengxi Diao, Fujiang Lin:
A Low-Power VCO based ADC with asynchronous sigma-delta modulator in 65nm CMOS. 38-39 - Sho Ikeda, Sang-yeop Lee, Shin Yonezawa, Yiming Fang, Motohiro Takayasu, Taisuke Hamada, Yosuke Ishikawa, Hiroyuki Ito, Noboru Ishihara, Kazuya Masu:
A 0.5-V 5.8-GHz low-power asymmetrical QPSK/OOK transceiver for wireless sensor network. 40-41 - Teerachot Siriburanon
A 58.3-to-65.4 GHz 34.2 mW sub-harmonically injection-locked PLL with a sub-sampling phase detection. 42-43 - Akira Okada, Abdul Raziz Junaidi, Yasuhiro Take, Atsutake Kosuge, Tadahiro Kuroda:
Circuit and package design for 44GB/s inductive-coupling DRAM/SoC interface. 44-45 - Li-Chung Hsu, Yasuhiro Take, Atsutake Kosuge, So Hasegawa, Junichiro Kadamoto, Tadahiro Kuroda:
Design and analysis for ThruChip design for manufacturing (DFM). 46-47 - Leibo Liu
A novel approach using a minimum cost maximum flow algorithm for fault-tolerant topology reconfiguration in NoC architectures. 48-53 - Peng Wang, Sheng Ma, Hongyi Lu, Zhiying Wang, Chen Li:
Adaptive remaining hop count flow control: Consider the interaction between packets. 54-60 - Takeshi Soga, Hiroshi Sasaki, Tomoya Hirao, Masaaki Kondo, Koji Inoue:
A flexible hardware barrier mechanism for many-core processors. 61-68 - Lian Zeng, Takahiro Watanabe:
A performance enhanced dual-switch Network-on-Chip architecture. 69-74 - Alireza Shafaei, Shuang Chen, Yanzhi Wang, Massoud Pedram:
A cross-layer framework for designing and optimizing deeply-scaled FinFET-based SRAM cells under process variations. 75-80 - Adam Teman
Controlled placement of standard cell memory arrays for high density and low power in 28nm FD-SOI. 81-86 - Jun Shiomi, Tohru Ishihara
Microarchitectural-level statistical timing models for near-threshold circuit design. 87-93 - Shengcheng Wang, Farshad Firouzi, Fabian Oboril, Mehdi Baradaran Tahoori:
Stress-aware P/G TSV planning in 3D-ICs. 94-99 - Chao Zhang, Guangyu Sun, Weiqi Zhang, Fan Mi, Hai Li
Quantitative modeling of racetrack memory, a tradeoff among area, performance, and power. 100-105 - Peng Gu, Boxun Li, Tianqi Tang, Shimeng Yu
Technological exploration of RRAM crossbar array for matrix-vector multiplication. 106-111 - Yang Zheng, Cong Xu, Yuan Xie:
Modeling framework for cross-point resistive memory design emphasizing reliability and variability issues. 112-117 - Ching-Yi Huang, Chian-Wei Liu, Chun-Yao Wang, Yung-Chih Chen, Suman Datta
A defect-aware approach for mapping reconfigurable Single-Electron Transistor arrays. 118-123 - Hyung Gyu Lee, Naehyuck Chang:
Powering the IoT: Storage-less and converter-less energy harvesting. 124-129 - Shao-Yi Chien
Distributed computing in IoT: System-on-a-chip for smart cameras as an example. 130-135 - James Williamson, Qi Liu, Fenglong Lu, Wyatt Mohrman, Kun Li, Robert P. Dick, Li Shang:
Data sensing and analysis: Challenges for wearables. 136-141 - Hang Lu, Guihai Yan, Yinhe Han, Ying Wang, Xiaowei Li
ShuttleNoC: Boosting on-chip communication efficiency by enabling localized power adaptation. 142-147 - Hui Li
Energy-efficient optical crossbars on chip with multi-layer deposited silicon. 148-153 - Julian J. H. Pontes, Pascal Vivet
Two-phase protocol converters for 3D asynchronous 1-of-n data links. 154-159 - Xiaohang Wang, Tengfei Wang, Terrence S. T. Mak, Mei Yang, Yingtao Jiang, Masoud Daneshtalab:
Fine-grained runtime power budgeting for networks-on-chip. 160-165 - Shuangchen Li, Ang Li, Yongpan Liu, Yuan Xie, Huazhong Yang:
Nonvolatile memory allocation and hierarchy optimization for high-level synthesis. 166-171 - Robert Wille
Reverse BDD-based synthesis for splitter-free optical circuits. 172-177 - Aaron Lye
Determining the minimal number of swap gates for multi-dimensional nearest neighbor quantum circuits. 178-183 - Zipeng Li, Tsung-Yi Ho
Design and optimization of 3D digital microfluidic biochips for the polymerase chain reaction. 184-189 - Lixue Xia
An accurate and low-cost PM2.5 estimation method based on Artificial Neural Network. 190-195 - Zhi Hu, Yibo Fan, Xiaoyang Zeng:
Iterative disparity voting based stereo matching algorithm and its hardware implementation. 196-201 - Yu-Wei Wu, Yiyu Shi, Sudip Roy, Tsung-Yi Ho
Obstacle-avoiding wind turbine placement for power-loss and wake-effect optimization. 202-207 - Haitong Tian, Hongbo Zhang, Zigang Xiao, Martin D. F. Wong
An efficient linear time triple patterning solver. 208-213 - Tiago Reimann, Cliff C. N. Sze, Ricardo Reis
Gate sizing and threshold voltage assignment for high performance microprocessor designs. 214-219 - Yasuhiro Takashima:
Analytical placement for rectilinear blocks. 220-225 - Eric Jia-Wei Fang, Terry Chi-Jih Shih, Darton Shen-Yu Huang:
IR to routing challenge and solution for interposer-based design. 226-230 - Anteneh Gebregiorgis, Mojtaba Ebrahimi, Saman Kiamehr, Fabian Oboril, Said Hamdioui, Mehdi Baradaran Tahoori:
Aging mitigation in memory arrays using self-controlled bit-flipping technique. 231-236 - Chang Liu, Xinghua Yang, Fei Qiao, Qi Wei, Huazhong Yang:
Design methodology for approximate accumulator based on statistical error model. 237-242 - Luca Gaetano Amarù, Gage Hills, Pierre-Emmanuel Gaillardon, Subhasish Mitra
Multiple Independent Gate FETs: How many gates do we need? 243-248 - Subhendu Roy, Mihir R. Choudhury, Ruchir Puri, David Z. Pan:
Polynomial time algorithm for area and power efficient adder synthesis in high-performance designs. 249-254 - Yusuke Matsunaga:
Accelerating SAT-based Boolean matching for heterogeneous FPGAs using one-hot encoding and CEGAR technique. 255-260 - Ji Li, Yanzhi Wang, Xue Lin, Shahin Nazarian, Massoud Pedram:
Negotiation-based task scheduling and storage control algorithm to minimize user's electric bills under dynamic prices. 261-266 - Matthias Kauer, Swaminathan Narayanaswamy, Sebastian Steinhorst
Many-to-many active cell balancing strategy design. 267-272 - Ta-Yang Huang, Chia-Jui Chang, Chung-Wei Lin, Sudip Roy, Tsung-Yi Ho
Intra-vehicle network routing algorithm for wiring weight and wireless transmit power minimization. 273-278 - Yusuke Sakumoto, Ittetsu Taniguchi
An autonomous decentralized mechanism for energy interchanges with accelerated diffusion based on MCMC. 279-284 - Atsushi Takahara:
ASP-DAC 2015 keynote speech II programmable network. 285 - Bei Yu, David Z. Pan, Tetsuaki Matsunawa, Xuan Zeng:
Machine learning and pattern matching in physical design. 286-293 - Fangming Ye, Krishnendu Chakrabarty
Self-learning and adaptive board-level functional fault diagnosis. 294-301 - Shupeng Sun, Xin Li:
Fast statistical analysis of rare failure events for memory circuits in high-dimensional variation space. 302-307 - Li-C. Wang
Data mining in functional test content optimization. 308-315 - Mimi Xie, Chen Pan, Jingtong Hu
Checkpoint-aware instruction scheduling for nonvolatile processor with multiple functional units. 316-321 - Linbo Long, Duo Liu, Xiao Zhu, Kan Zhong, Zili Shao
Balloonfish: Utilizing morphable resistive memory in mobile virtualization. 322-327 - Yanbin Li, Xin Li, Lei Ju, Zhiping Jia:
A three-stage-write scheme with flip-bit for PCM main memory. 328-333 - Min Huang, Yi Wang
A Garbage Collection Aware Stripping method for Solid-State Drives. 334-339 - Renhai Chen, Yi Wang
Unified non-volatile memory and NAND flash memory architecture in smartphones. 340-345 - Palkesh Jain, Sachin S. Sapatnekar
A retargetable and accurate methodology for logic-IP-internal electromigration assessment. 346-351 - Hai-Bao Chen, Sheldon X.-D. Tan, Xin Huang, Valeriy Sukharev
New electromigration modeling and analysis considering time-varying temperature and current densities. 352-357 - Zahi Moudallal, Farid N. Najm:
Generating circuit current constraints to guarantee power grid safety. 358-365 - Aadithya V. Karthik, Sayak Ray, Jaijeet Roychowdhury:
BEE: Predicting realistic worst case and stochastic eye diagrams by accounting for correlated bitstreams and coding strategies. 366-371 - Chung-Hao Tsai, Wai-Kei Mak:
A fast parallel approach for common path pessimism removal. 372-377 - Chau-Chin Huang, Chien-Hsiung Chiou, Kai-Han Tseng, Yao-Wen Chang
Detailed-Routing-Driven analytical standard-cell placement. 378-383 - Shih-Ying Liu, Tung-Chieh Chen, Hung-Ming Chen:
An approach to anchoring and placing high performance custom digital designs. 384-389 - Po-Ya Hsu, Yao-Wen Chang
Non-stitch triple patterning-aware routing based on conflict graph pre-coloring. 390-395 - Shao-Yun Fang:
Cut mask optimization with wire planning in self-aligned multiple patterning full-chip routing. 396-401 - Ran Zhang, Tieyuan Pan, Li Zhu, Takahiro Watanabe:
A length matching routing method for disordered pins in PCB design. 402-407 - Hidekazu Nishimura:
Systems modeling for additional development in automotive E/E architecture. 408-409 - Nau Ozaki, Masato Uchiyama, Yasuki Tanabe, Shuichi Miyazaki, Takaaki Sawada, Takanori Tamai, Moriyasu Banno:
Implementation and evaluation of image recognition algorithm for an intelligent vehicle using heterogeneous multi-core SoC. 410-415 - Khalid Hussein, Akira Fujita, Katsumi Sato:
Trend in power devices for electric and hybrid electric vehicles. 416 - Haifeng Xu, Yong Li, Rami G. Melhem, Alex K. Jones
Multilane Racetrack caches: Improving efficiency through compression and independent shifting. 417-422 - Zimeng Zhou, Lei Ju, Zhiping Jia, Xin Li:
Managing hybrid on-chip scratchpad and cache memories for multi-tasking embedded systems. 423-428 - Guantao Liu, Tim Schmidt, Rainer Dömer, Ajit Dingankar, Desmond Kirkpatrick:
Optimizing thread-to-core mapping on manycore platforms with distributed Tag Directories. 429-434 - Mohammad Shihabul Haque, Ang Li, Akash Kumar, Qingsong Wei:
Accelerating non-volatile/hybrid processor cache design space exploration for application specific embedded systems. 435-440 - Ying-Chih Wang, Shihui Yin, Minhee Jun, Xin Li, Lawrence T. Pileggi, Tamal Mukherjee
Accurate passivity-enforced macromodeling for RF circuits via iterative zero/pole update based on measurement data. 441-446 - Volker Meyer zu Bexten, Markus Tristl, Göran Jerke, Hartmut Marquardt, Dina Medhat:
Physical verification flow for hierarchical analog ic design constraints. 447-453 - Zhijian Pan, Chuan Qin, Zuochang Ye, Yan Wang:
Automatic design for analog/RF front-end system in 802.11ac receiver. 454-459 - Qicheng Huang, Xiao Li, Fan Yang, Xuan Zeng, Xin Li:
SIPredict: Efficient post-layout waveform prediction via System Identification. 460-465 - Juyeon Kim, Taewhan Kim:
Useful clock skew scheduling using adjustable delay buffers in multi-power mode designs. 466-471 - Rickard Ewetz, Shankarshana Janarthanan, Cheng-Kok Koh:
Fast clock skew scheduling based on sparse-graph algorithms. 472-477 - Wulong Liu, Guoqing Chen, Yu Wang, Huazhong Yang:
Modeling and optimization of low power resonant clock mesh. 478-483 - Seyong Ahn, Minseok Kang, Marios C. Papaefthymiou, Taewhan Kim:
Synthesis of resonant clock networks supporting dynamic voltage / frequency scaling. 484-489 - Xiaoxiao Liu
An efficient STT-RAM-based register file in GPU architectures. 490-495 - Masashi Tawada, Shinji Kimura, Masao Yanagisawa, Nozomu Togawa
A bit-write reduction method based on error-correcting codes for non-volatile memories. 496-501 - Mengying Zhao, Yuan Xue, Chengmo Yang, Chun Jason Xue
Minimizing MLC PCM write energy for free through profiling-based state remapping. 502-507 - Hoda Aghaei Khouzani
Improving performance and lifetime of DRAM-PCM hybrid main memory through a proactive page allocation strategy. 508-513 - Songwei Pei, Ye Geng, Huawei Li, Jun Liu, Song Jin:
Enhanced LCCG: A novel test clock generation scheme for faster-than-at-speed delay testing. 514-519 - Liang-Che Li, Wen-Hsuan Hsu, Kuen-Jong Lee, Chun-Lung Hsu:
An efficient 3D-IC on-chip test framework to embed TSV testing in memory BIST. 520-525 - Nima Aghaee, Zebo Peng, Petru Eles:
An integrated temperature-cycling acceleration and test technique for 3D stacked ICs. 526-531 - Sergej Deutsch, Krishnendu Chakrabarty
Software-based test and diagnosis of SoCs using embedded and wide-I/O DRAM. 532-537 - Minjie Lv
Logic-DRAM co-design to efficiently repair stacked DRAM with unused spares. 538-543 - Jiwoo Pak, Bei Yu, David Z. Pan:
Electromigration-aware redundant via insertion. 544-549 - Yuankai Chen, Hai Zhou:
Synthesis of resilient circuits from guarded atomic actions. 550-555 - Yen-Lung Chen, Wei Wu, Chien-Nan Jimmy Liu, Lei He:
Incremental Latin hypercube sampling for lifetime stochastic behavioral modeling of analog circuits. 556-561 - Noriko Arai:
ASP-DAC 2015 keynote speech III: When and how will an AI be smart enough to design? 562 - Amirali Ghofrani, Miguel Angel Lastras-Montaño, Kwang-Ting Cheng
Toward large-scale access-transistor-free memristive crossbars. 563-568 - Meng-Fan Chang, Albert Lee, Chien-Chen Lin, Mon-Shu Ho, Ping-Cheng Chen, Chia-Chen Kuo, Ming-Pin Chen, Pei-Ling Tseng, Tzu-Kun Ku, Chien-Fu Chen
Read circuits for resistive memory (ReRAM) and memristor-based nonvolatile Logics. 569-574 - Sung Hyun Jo, Tanmay Kumar, Mehdi Asnaashari, Wei D. Lu
3D ReRAM with Field Assisted Super-Linear Threshold (FASTTM) Selector technology for super-dense, low power, low latency data storage systems. 575 - Jinfeng Kang, Haitong Li, Peng Huang, Zhe Chen, Bin Gao, Xiaoyan Liu, Zizhen Jiang, H.-S. Philip Wong:
Modeling and design optimization of ReRAM. 576-581 - Biao Hu, Kai Huang, Gang Chen, Alois C. Knoll
Evaluation of runtime monitoring methods for real-time event streams. 582-587 - Li-Chun Chen, Hsin-I Wu, Ren-Song Tsay:
Automatic timing-coherent transactor generation for mixed-level simulations. 588-593 - Hsuan-Ming Chou, Hong-Chang Wu, Yi-Chiao Chen, Jean Tsao, Shih-Chieh Chang:
Hybrid coverage assertions for efficient coverage analysis across simulation and emulation environments. 594-599 - Luis Gabriel Murillo
SWAT: Assertion-based debugging of concurrency issues at system level. 600-605 - Che-Wei Chang, Rainer Dömer:
Communication protocol analysis of transaction-level models using Satisfiability Modulo Theories. 606-611 - Laura A. Rozo Duque, Chengmo Yang:
Guiding fault-driven adaption in multicore systems through a reliability-aware static task schedule. 612-617 - Cheng Tan
Approximation-aware scheduling on heterogeneous multi-core architectures. 618-623 - Martin Becker, Alejandro Masrur, Samarjit Chakraborty
Composing real-time applications from communicating black-box components. 624-629 - Zaid Al-bayati, Qingling Zhao, Ahmed Youssef, Haibo Zeng, Zonghua Gu:
Enhanced partitioned scheduling of Mixed-Criticality Systems on multicore platforms. 630-635 - Jiaxing Zhang, Sanyuan Tang, Gunar Schirner:
Reducing Dynamic Dispatch Overhead (DDO) of SLDL-synthesized embedded software. 636-643 - Zigang Xiao, Yuelin Du, Martin D. F. Wong
Contact pitch and location prediction for Directed Self-Assembly template verification. 644-651 - Yunfeng Yang, Wai-Shing Luk, Hai Zhou, Changhao Yan, Xuan Zeng, Dian Zhou:
Layout decomposition co-optimization for hybrid e-beam and multiple patterning lithography. 652-657 - Daifeng Guo, Yuelin Du, Martin D. F. Wong
Polynomial time optimal algorithm for stencil row planning in e-beam lithography. 658-664 - Yukihide Kohira, Tomomi Matsui
Fast mask assignment using positive semidefinite relaxation in LELECUT triple patterning lithography. 665-670 - Shao-Yun Fang, Yi-Shu Tai, Yao-Wen Chang
Layout decomposition for Spacer-is-Metal (SIM) self-aligned double patterning. 671-676 - Keiya Motohashi:
The prospects of next generation television - Japan's initiative to 2020. 677-679 - Takeshi Kumakura:
8K LCD: Technologies and challenges toward the realization of SUPER Hi-VISION TV. 680-683 - Daisuke Murakami, Yuki Soga, Daisuke Imoto, Yoshiharu Watanabe, Takashi Yamada:
The world's 1st Complete-4K SoC solution with hybrid memory system. 684-686 - Mitsuo Ikeda:
H.265/HEVC encoder for UHDTV. 687-688 - Hongwei Wang, Ziyuan Zhu, Jinglin Shi, Yongtao Su:
An accurate ACOSSO metamodeling technique for processor architecture design space exploration. 689-694 - Josef Schneider, Jorgen Peddersen, Sri Parameswaran
Speeding up single pass simulation of PLRUt caches. 695-700 - Xi Zhang, Haris Javaid, Muhammad Shafique
ADAPT: An adaptive manycore methodology for software pipelined applications. 701-706 - Anastasiia Butko, Rafael Garibotti
A trace-driven approach for fast and accurate simulation of manycore architectures. 707-712 - Mohammed Shemsu Nesro, Lizhong Sun, Ibrahim M. Elfadel
Compact modeling of microbatteries using behavioral linearization and model-order reduction. 713-718 - Yan Zhu, Sheldon X.-D. Tan:
GPU-accelerated parallel Monte Carlo analysis of analog circuits by hierarchical graph-based solver. 719-724 - Hyun-Sek Lukas Lee, Matthias Althoff, Stefan Hoelldampf, Markus Olbrich, Erich Barke:
Automated generation of hybrid system models for reachability analysis of nonlinear analog circuits. 725-730 - Shoichi Iizuka, Yuma Higuchi, Masanori Hashimoto
Area efficient device-parameter estimation using sensitivity-configurable ring oscillator. 731-736 - Zelong Sun, Li Jiang, Qiang Xu
On test syndrome merging for reasoning-based board-level functional fault diagnosis. 737-742 - Mojtaba Ebrahimi, Razi Seyyedi, Liang Chen, Mehdi Baradaran Tahoori:
Event-driven transient error propagation: A scalable and accurate soft error rate estimation approach. 743-748 - Daisuke Fujimoto, Makoto Nagata
A novel methodology for testing hardware security and trust exploiting On-Chip Power noise Measurement. 749-754 - Nicole Lesperance, Shrikant Kulkarni, Kwang-Ting Cheng
Hardware Trojan detection using exhaustive testing of k-bit subspaces. 755-760 - Zih-Ci Huang, Chi-Kang Chen, Ren-Song Tsay:
AROMA: A highly accurate microcomponent-based approach for embedded processor power analysis. 761-766 - Yu Peng, Shouyi Yin, Leibo Liu
Battery-aware mapping optimization of loop nests for CGRAs. 767-772 - Jinho Lee
THOR: Orchestrated thermal management of cores and networks in 3D many-core architectures. 773-778 - Jianlei Yang, Liwei Ma
Early stage real-time SoC power estimation using RTL instrumentation. 779-784 - Qiaosha Zou, Matthew Poremba, Rui He, Wei Yang, Junfeng Zhao, Yuan Xie:
Heterogeneous architecture design with emerging 3D and non-volatile memory technologies. 785-790 - Zhehui Wang
Alleviate chip I/O pin constraints for multicore processors through optical interconnects. 791-796 - Ting-Shuo Hsu, Jun-Lin Chiu, Chao-Kai Yu, Jing-Jia Liou:
A fast and accurate network-on-chip timing simulator with a flit propagation model. 797-802 - Chih-Tsun Huang, Kuan-Chun Tasi, Jun-Shen Lin, Hsiao-Wei Chien:
Application-level embedded communication tracer for many-core systems. 803-808 - Sixing Lu, Minjun Seo, Roman Lysecky:
Timing-based anomaly detection in embedded systems. 809-814 - Carson Dunbar, Gang Qu:
Satisfiability Don't Care condition based circuit fingerprinting techniques. 815-820 - Soroush Khaleghi, Kai Da Zhao, Wenjing Rao
IC Piracy prevention via Design Withholding and Entanglement. 821-826 - Lingxiao Wei, Jie Zhang, Feng Yuan, Yannan Liu, Junfeng Fan, Qiang Xu
Vulnerability analysis for crypto devices against probing attack. 827-832
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